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8 bit microcontroller tlcs-870/c series TMP86FS49BFG
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2007 toshiba corporation all rights reserved
TMP86FS49BFG differences among products differences in functions note 1: the products with flash memory (86fs49, 86fs49a, 86fs 49b) contain the flash control register (flscr) at 0fffh in the dbr area. the products with mask rom or otp and the em ulation chip do not have the flscr register. in these devices, therefore, a program that accesse s the flscr register cannot function pr operly (executes differently as in the case of a flash product). note 2: in this data sheet,the following pin names and register names have been changed from the data sheet of the old edition. although the names have been changed, their functions remain the same. 86ch49 86cm49 86pm49 86cs49 86fs49 86fs49a 86fs49b rom 16 kbytes (mask) 32 kbytes (mask) 32 kbytes (otp) 60 kbytes (mask) 60 kbytes (flash) ram 512 bytes 1 kbyte 1 kbyte 2 kbytes 2 kbytes dbr(note1) 128 bytes (flash control register not contained) 128 bytes (flash control register contained) i/o 56 pins high-current port 13 pins (sink open drain) interrupt external: 5 interrupts, internal: 19 interrupts timer/counter 16-bit: 2 channels 8-bit: 4 channels uart 2 channels sio 2 channels i 2 c 1 channel key-on wake-up 4 channels 10-bit ad converter (note2) 16 channels flash security n.a. read protect read/write protect structurer of test pin absolute maximum rating of power supply(vdd) 6.5v 6.0v emulation chip tmp86c949xb package qfp64- p-1414- 0.80a qfp64-p-1414-0.80a lqfp64-p-1010-0.50d sdip64-p-750-1.78 qfp64-p-1414-0.80a lqfp64-p-1010-0.50d ? vdd r in r r without pull down resister without protect diode on the vdd side vdd r in r r without pull down resister without protect diode on the vdd side r vdd without pull down resister r without pull down resister without protect diode on the vdd side
TMP86FS49BFG old name new name a d c o n v e r t e r analog input pin name p60(ain00) p61(ain01) p62(ain02) p63(ain03) p64(ain04) p65(ain05) p66(ain06) p67(ain07) p70(ain10) p71(ain11) p72(ain12) p73(ain13) p74(ain14) p75(ain15) p76(ain16) p77(ain17) p60(ain0) p61(ain1) p62(ain2) p63(ain3) p64(ain4) p65(ain5) p66(ain6) p67(ain7) p70(ain8) p71(ain9) p72(ain10) p73(ain11) p74(ain12) p75(ain13) p76(ain14) p77(ain15) adccr1 register function name 0000:ain00 0001:ain01 0010:ain02 0011:ain03 0100:ain04 0101:ain05 0110:ain06 0111:ain07 1000:ain10 1001:ain11 1010:ain12 1011:ain13 1100:ain14 1101:ain15 1110:ain16 1111:ain17 0000:ain0 0001:ain1 0010:ain2 0011:ain3 0100:ain4 0101:ain5 0110:ain6 0111:ain7 1000:ain8 1001:ain9 1010:ain10 1011:ain11 1100:ain12 1101:ain13 1110:ain14 1111:ain15
TMP86FS49BFG differences in elect rical characteristics note 1: with the 86cs49, the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 2.0 v. note 2: with the 86fs49, the supply voltage vdd is specified as two separate ranges. while the mcu is operating, do not change the supply voltage from range (a) to range (b) or from range (b) to range (a). note 3: with the 86fs49a, the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 3.0 v. note 4: with the 86fs49a/b, when a program is executing in t he flash memory or when data is being read from the flash memory, the flash memory operates in an intermittent manner causing peak currents in the flash memory momentarily, as shown in figure. in this case, th e supply current idd (in normal1, normal2 and slow1 modes) is defined as the sum of the average peak current and mcu current. note 5: about the measurement condition of supply current, v il level of test pin is deffrent between 86fs49b and the other 86xx49 series mcus. the supply current is defined as follows; v il of test pin : v il 0.1v (86fs49b), v il 0.2v (others) it is described in the section "electrical char acteristics" of tmp86fs49b in detail. 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] 2.0 (a) (b) (note 1) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (b) (note 2) (a) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 (a) (b) (note 3) [mhz] [v] 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 (a) [mhz] [v] 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 2 4.2 8 16 [mhz] [v] (a) (a) 1.8v to 5.5v (-40 to 85c) (a) 2.0v to 5.5v (-40 to 85c) (a) 4.5v to 5.5v (-40 to 85c) (a) 3.0v to 5.5v (-40 to 85c) (a ) 2.7v to 5.5v (-40 to 85c) (b) 1.8v to 2.0v (-20 to 85c) (b) 3.0v to 3.6v (-40 to 85c) (b) 2.7v to 3.0v (-20 to 85c) 86ch49 86cm49 86cs49 86fs49 86fs49a 86fs49b 86pm49 - - (a) 4.5v to 5.5v (-10 to 40c) - - (a) 4.5v to 5.5v (-10 to 40c) - - - - (note 4) operating current operating condition (serial prom mode) erase / program read / fetch operating condition (mcu mode) operating current varies with each product. for details, refer to the datasheet (electrical characteristics) of each product. ( note 5) n program counter (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu curren t intermittent operat ion of flash memory
TMP86FS49BFG
revision history date revision 2007/8/24 1 first release

i table of contents differences among products TMP86FS49BFG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 memory address map ............................................................................................................................... 9 2.1.2 program memory (flash) .......................................................................................................................... 9 2.1.3 data memory (ram) ............................................................................................................................... .. 9 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 clock generator ............................................................................................................................... ....... 10 2.2.2 timing generator ............................................................................................................................... ..... 12 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 13 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ......................................................................................................................... 18 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 external reset input ............................................................................................................................... 31 2.3.2 address trap reset ............................................................................................................................... ... 32 2.3.3 watchdog timer reset .............................................................................................................................. 32 2.3.4 system clock reset ............................................................................................................................... ... 32 3. interrupt control circuit 3.1 interrupt latches (il23 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 36 3.2.2 individual interrupt enable flags (ef23 to ef4) ...................................................................................... 37 note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 39 3.3.2 saving/restoring general-purpose registers ............................................................................................ 40 3.3.2.1 using push and pop instructions
ii 3.3.2.2 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 41 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1 address error detection .......................................................................................................................... 42 3.4.2 debugging ............................................................................................................................... ............... 42 3.5 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. i/o ports 5.1 port p0 (p07 to p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 port p1 (p17 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4 port p3 (p37 to p30) (large current port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5 port p4 (p47 to p40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.6 port p5 (p54 to p50) (large current port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.7 port p6 (p67 to p60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.8 port p7 (p77 to p70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 66 6.2.2 watchdog timer enable ......................................................................................................................... 67 6.2.3 watchdog timer disable ........................................................................................................................ 68 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 68 6.2.5 watchdog timer reset ........................................................................................................................... 69 6.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.1 selection of address trap in internal ram (atas) ................................................................................ 70 6.3.2 selection of operation at address trap (atout) .................................................................................. 70 6.3.3 address trap interrupt (intatrap) ....................................................................................................... 70 6.3.4 address trap reset ............................................................................................................................... . 71 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.1.1 configuration ............................................................................................................................... ........... 73 7.1.2 control ............................................................................................................................... ..................... 73 7.1.3 function ............................................................................................................................... ................... 74 7.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2.1 configuration ............................................................................................................................... ........... 75 7.2.2 control ............................................................................................................................... ..................... 75
iii 8. 16-bit timercounter 1 (tc1) 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.3.1 timer mode ............................................................................................................................... .............. 80 8.3.2 external trigger timer mode .................................................................................................................. 82 8.3.3 event counter mode ............................................................................................................................... 84 8.3.4 window mode ............................................................................................................................... .......... 85 8.3.5 pulse width measurement mode ............................................................................................................ 86 8.3.6 programmable pulse generate (ppg) output mode ............................................................................. 89 9. 16-bit timer/counter2 (tc2) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3.1 timer mode ............................................................................................................................... .............. 95 9.3.2 event counter mode ............................................................................................................................... . 97 9.3.3 window mode ............................................................................................................................... .......... 97 10. 8-bit timercounter (tc3, tc4) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.3.1 8-bit timer mode (tc3 and 4) ............................................................................................................ 105 10.3.2 8-bit event counter mode (tc3, 4) .................................................................................................... 106 10.3.3 8-bit programmable divider output (pdo) mode (tc3, 4) ................................................................. 106 10.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) .............................................................. 109 10.3.5 16-bit timer mode (tc3 and 4) .......................................................................................................... 111 10.3.6 16-bit event counter mode (tc3 and 4) ............................................................................................ 112 10.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) ...................................................... 112 10.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ........................................... 115 10.3.9 warm-up counter mode ..................................................................................................................... 117 10.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 10.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 11. 8-bit timercounter (tc5, tc6) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.3.1 8-bit timer mode (tc5 and 6) ............................................................................................................ 125 11.3.2 8-bit event counter mode (tc5, 6) .................................................................................................... 126 11.3.3 8-bit programmable divider output (pdo) mode (tc5, 6) ................................................................. 126 11.3.4 8-bit pulse width modulation (pwm) output mode (tc5, 6) .............................................................. 129 11.3.5 16-bit timer mode (tc5 and 6) .......................................................................................................... 131 11.3.6 16-bit event counter mode (tc5 and 6) ............................................................................................ 132 11.3.7 16-bit pulse width modulation (pwm) output mode (tc5 and 6) ...................................................... 132 11.3.8 16-bit programmable pulse generate (ppg) output mode (tc5 and 6) ........................................... 135 11.3.9 warm-up counter mode ..................................................................................................................... 137 11.3.9.1 low-frequency warm-up counter mode
iv (normal1 normal2 slow2 slow1) 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 12. asynchronous serial interface (uart1 ) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.8.1 data transmit operation .................................................................................................................... 144 12.8.2 data receive operation ..................................................................................................................... 144 12.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.9.1 parity error ............................................................................................................................... ........... 145 12.9.2 framing error ............................................................................................................................... ....... 145 12.9.3 overrun error ............................................................................................................................... ....... 145 12.9.4 receive data buffer full ..................................................................................................................... 146 12.9.5 transmit data buffer empty ............................................................................................................... 146 12.9.6 transmit end flag .............................................................................................................................. 147 13. asynchronous serial interface (uart2 ) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 13.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 13.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 13.8.1 data transmit operation .................................................................................................................... 154 13.8.2 data receive operation ..................................................................................................................... 154 13.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.9.1 parity error ............................................................................................................................... ........... 155 13.9.2 framing error ............................................................................................................................... ....... 155 13.9.3 overrun error ............................................................................................................................... ....... 155 13.9.4 receive data buffer full ..................................................................................................................... 156 13.9.5 transmit data buffer empty ............................................................................................................... 156 13.9.6 transmit end flag .............................................................................................................................. 157 14. synchronous serial interface (sio1) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.3.1 serial clock ............................................................................................................................... .......... 162 14.3.1.1 clock source 14.3.1.2 shift edge 14.3.2 transfer bit direction ........................................................................................................................... 164 14.3.2.1 transmit mode
v 14.3.2.2 receive mode 14.3.2.3 transmit/receive mode 14.3.3 transfer modes ............................................................................................................................... .... 165 14.3.3.1 transmit mode 14.3.3.2 receive mode 14.3.3.3 transmit/receive mode 15. synchronous serial interface (sio2) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.3.1 serial clock ............................................................................................................................... .......... 180 15.3.1.1 clock source 15.3.1.2 shift edge 15.3.2 transfer bit direction ........................................................................................................................... 182 15.3.2.1 transmit mode 15.3.2.2 receive mode 15.3.2.3 transmit/receive mode 15.3.3 transfer modes ............................................................................................................................... .... 183 15.3.3.1 transmit mode 15.3.3.2 receive mode 15.3.3.3 transmit/receive mode 16. serial bus interface(i2c bus) ver.-d (sbi) 16.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.4 the data format in the i2c bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.5 i2c bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.5.1 acknowledgement mode specification ................................................................................................ 199 16.5.1.1 acknowledgment mode (ack = ?1?) 16.5.1.2 non-acknowledgment mode (ack = ?0?) 16.5.2 number of transfer bits ....................................................................................................................... 200 16.5.3 serial clock ............................................................................................................................... .......... 200 16.5.3.1 clock source 16.5.3.2 clock synchronization 16.5.4 slave address and address re cognition mode specification ............................................................... 201 16.5.5 master/slave selection ........................................................................................................................ 201 16.5.6 transmitter/receiver selection ............................................................................................................. 201 16.5.7 start/stop condition generation ........................................................................................................... 202 16.5.8 interrupt service request and cancel ................................................................................................... 202 16.5.9 setting of i2c bus mode ..................................................................................................................... 203 16.5.10 arbitration lost detection monitor ...................................................................................................... 203 16.5.11 slave address match detection monitor ............................................................................................ 204 16.5.12 general call detection monitor .................................................................................................. 204 16.5.13 last received bit monitor ................................................................................................................... 204 16.6 data transfer of i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6.1 device initialization ............................................................................................................................. 2 05 16.6.2 start condition and slave address generation ..................................................................................... 205 16.6.3 1-word data transfer ............................................................................................................................ 20 5 16.6.3.1 when the mst is ?1? (master mode) 16.6.3.2 when the mst is ?0? (slave mode) 16.6.4 stop condition generation ................................................................................................................... 208 16.6.5 restart ............................................................................................................................... ................. 209 17. 10-bit ad converter (adc) 17.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
vi 17.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 17.3.1 software start mode ........................................................................................................................... 215 17.3.2 repeat mode ............................................................................................................................... ....... 215 17.3.3 register setting ............................................................................................................................... . 216 17.4 stop/slow modes during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 218 17.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 17.6.1 restrictions for ad conversion interrupt (intadc) usage ................................................................. 219 17.6.2 analog input pin voltage range ........................................................................................................... 219 17.6.3 analog input shared pins .................................................................................................................... 219 17.6.4 noise countermeasure ....................................................................................................................... 219 18. key-on wakeup (kwu) 18.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19. flash memory 19.1 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 19.1.1 flash memory command sequence execution control (flscr) ..................................... 224 19.1.2 flash memory bank select control (flscr) ................................................................ 224 19.2 command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 19.2.1 byte program ............................................................................................................................... ....... 225 19.2.2 sector erase (4-kbyte erase) ............................................................................................................. 225 19.2.3 chip erase (all erase) ........................................................................................................................ 226 19.2.4 product id entry ............................................................................................................................... .. 226 19.2.5 product id exit ............................................................................................................................... ..... 226 19.2.6 security program ............................................................................................................................... . 226 19.3 toggle bit (d6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.4 access to the flash memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 19.4.1 flash memory control in the serial prom mode ............................................................................... 228 19.4.1.1 how to write to the flash memory by executing the contro l program in the ram area (in the ram loader mode within the serial prom mode) 19.4.2 flash memory control in the mcu mode ............................................................................................ 230 19.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) 20. serial prom mode 20.1 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 20.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 20.3 serial prom mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 20.3.1 serial prom mode control pins ........................................................................................................ 234 20.3.2 pin function ............................................................................................................................... ......... 234 20.3.3 example connection for on-board writing ......................................................................................... 235 20.3.4 activating the serial prom mode ...................................................................................................... 236 20.4 interface specifications for uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 20.5 operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 20.6 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 20.6.1 flash memory erasing mode (operating command: f0h) ................................................................. 241 20.6.2 flash memory writing mode (operation command: 30h) .................................................................. 243 20.6.3 ram loader mode (operation command: 60h) ................................................................................ 246
vii 20.6.4 flash memory sum output mode (operation command: 90h) ......................................................... 248 20.6.5 product id code output mode (operation command: c0h) .............................................................. 249 20.6.6 flash memory status output mode (operation command: c3h) ...................................................... 251 20.6.7 flash memory security program setting mode (operation command: fah) ..................................... 252 20.7 error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 20.8 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 20.8.1 calculation method ............................................................................................................................. 2 54 20.8.2 calculation data ............................................................................................................................... ... 255 20.9 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10 passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10.1 password string ............................................................................................................................... . 257 20.10.2 handling of password error .............................................................................................................. 257 20.10.3 password management during program development .................................................................... 257 20.11 product id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.12 flash memory status code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.13 specifying the erasure area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.14 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 20.15 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 21. input/output circuit 21.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 21.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 22. electrical characteristics 22.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 22.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 22.2.1 mcu mode (flash programming or erasing) ..................................................................................... 268 22.2.2 mcu mode (except flash progra mming or erasing) ......................................................................... 268 22.2.3 serial prom mode ............................................................................................................................. 2 69 22.3 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 22.4 ad characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 22.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 22.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 22.6.1 write/retention characteristics .......................................................................................................... 273 22.7 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 22.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 23. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/c (lsi).
viii
page 1 TMP86FS49BFG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. TMP86FS49BFG the TMP86FS49BFG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of flash memory. it is pin-compatible with the tmp86ch49fg/cm49fg/cs49fg (mask rom version). the TMP86FS49BFG can realize operat ions equivalent to those of the tmp86ch49fg/cm49fg/cs49fg by pro- gramming the on-chip flash memory. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 24interrupt sources (external : 5 internal : 19) 3. input / output ports (56 pins) large current output: 13pins (typ. 20ma), led direct drive 4. watchdog timer 5. prescaler - time base timer - divider output function 6. 16-bit timer counter: 1 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 16-bit timer counter: 1 ch - timer, event counter, window modes product no. rom (flash) ram package maskrom mcu emulation chip TMP86FS49BFG 61440 bytes 2048 bytes qfp64-p-1414-0.80a tmp86ch49fg/ cm49fg/cs49fg tmp86c949xb
page 2 1.1 features TMP86FS49BFG 8. 8-bit timer counter : 4 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 9. 8-bit uart : 2 ch 10. high-speed sio: 2ch 11. serial bus interface(i 2 c bus): 1ch 12. 10-bit successive approximation type ad converter - analog input: 16 ch 13. key-on wakeup : 4 ch 14. clock operation single clock mode dual clock mode 15. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr. idle1 mode: cpu stops and peripherals operate us ing high frequency clock. release by interru- puts(cpu restarts). idle2 mode: cpu stops and peripherals operate usin g high and low frequency clock. release by inter- ruputs. (cpu restarts). sleep0 mode: cpu stops, and only the time-based-t imer(tbt) on peripherals operate using low fre- quency clock.release by falling edge of th e source clock which is set by tbtcr. sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interru- put.(cpu restarts). sleep2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruput. 16. wide operation voltage: 4.5 v to 5.5 v at 16 mhz /32.768 khz 2.7 v to 5.5 v at 8 mhz /32.768 khz
page 3 TMP86FS49BFG 1.2 pin assignment figure 1-1 pin assignment vss xout test vdd (xtin) p21 (xtout) p22 reset ( stop / int5 ) p20 ( int0 ) p00 (txd1) p02 (si1) p04 (int1) p03 (so1) p05 ( sck1 ) p06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p65(ain5/stop1) p67(ain7/stop3) p70(ain8) p72(ain10) p71(ain9) p74(ain12) p73(ain11) p66(ain6/stop2) p14 (tc4/ pdo4/pwm4/ppg4 ) p13 (tc3/ pdo3/pwm3 ) p12 ( ppg ) p11 ( dvo ) p10 (tc1) p47 p46 ( sck2 ) p45 (so2) (boot/rxd1) p01 xin p07(int2) avdd p60(ain0) p61(ain1) p64(ain4/stop0) p62(ain2) varef p63(ain3) p44 (si2) p43 p42 (txd2) p41 (rxd2) p40 p77 (ain15) p76 (ain14) p75 (ain13) (int3/tc2) p15 ( pdo5/pwm5 /tc5) p16 ( pdo6/pwm6/ppg6 /tc6) p17 (scl) p50 (sda) p51 p52 p53 p54 p30 p31 p32 p33 p34 p35 p36 p37
page 4 1.3 block diagram TMP86FS49BFG 1.3 block diagram figure 1-2 block diagram
page 5 TMP86FS49BFG 1.4 pin names and functions the TMP86FS49BFG has mcu mode, parallel prom mode , and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/3) pin name pin number input/output functions p07 int2 17 io i port07 external interrupt 2 input p06 sck1 16 io io port06 serial clock input/output 1 p05 so1 15 io o port05 serial data output 1 p04 si1 14 io i port04 serial data input 1 p03 int1 13 io i port03 external interrupt 1 input p02 txd1 12 io o port02 uart data output 1 p01 rxd1 boot 11 io i i port01 uart data input 1 serial prom mode control input p00 int0 10 io i port00 external interrupt 0 input p17 tc6 pdo6/pwm6/ppg6 51 io i o port17 tc6 input pdo6/pwm6/ppg6 output p16 tc5 pdo5/pwm5 50 io i o port16 tc5 input pdo5/pwm5 output p15 tc2 int3 49 io i i port15 tc2 input external interrupt 3 input p14 tc4 pdo4/pwm4/ppg4 48 io i o port14 tc4 input pdo4/pwm4/ppg4 output p13 tc3 pdo3/pwm3 47 io i o port13 tc3 input pdo3/pwm3 output p12 ppg 46 io o port12 ppg output p11 dvo 45 io o port11 divider output p10 tc1 44 io i port10 tc1 input p22 xtout 7 io o port22 resonator connecting pins(32.768 khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768 khz) for inputting external clock
page 6 1.4 pin names and functions TMP86FS49BFG p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input p37 64 io port37 p36 63 io port36 p35 62 io port35 p34 61 io port34 p33 60 io port33 p32 59 io port32 p31 58 io port31 p30 57 io port30 p47 43 io port47 p46 sck2 42 io io port46 serial clock input/output 2 p45 so2 41 io o port45 serial data output 2 p44 si2 40 io i port44 serial data input 2 p43 39 io port43 p42 txd2 38 io o port42 uart data output 2 p41 rxd2 37 io i port41 uart data input 2 p40 36 io port40 p54 56 io port54 p53 55 io port53 p52 54 io port52 p51 sda 53 io io port51 i2c bus data p50 scl 52 io io port50 i2c bus clock p67 ain7 stop3 27 io i i port67 analog input7 stop3 input p66 ain6 stop2 26 io i i port66 analog input6 stop2 input p65 ain5 stop1 25 io i i port65 analog input5 stop1 input p64 ain4 stop0 24 io i i port64 analog input4 stop0 input table 1-1 pin names and functions(2/3) pin name pin number input/output functions
page 7 TMP86FS49BFG p63 ain3 23 io i port63 analog input3 p62 ain2 22 io i port62 analog input2 p61 ain1 21 io i port61 analog input1 p60 ain0 20 io i port60 analog input0 p77 ain15 35 io i port77 analog input15 p76 ain14 34 io i port76 analog input14 p75 ain13 33 io i port75 analog input13 p74 ain12 32 io i port74 analog input12 p73 ain11 31 io i port73 analog input11 p72 ain10 30 io i port72 analog input10 p71 ain9 29 io i port71 analog input9 p70 ain8 28 io i port70 analog input8 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. varef 18 i analog base voltage input pin for a/d conversion avdd 19 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(3/3) pin name pin number input/output functions
page 8 1.4 pin names and functions TMP86FS49BFG
page 9 TMP86FS49BFG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FS49BFG memory is composed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64 -kbyte address space. figure 2-1 shows the TMP86FS49BFG memory address map. figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FS49BFG has a 61440 bytes (address 1000h to ffffh) of program memory (flash ). 2.1.3 data memory (ram) the TMP86FS49BFG has 2048 bytes (address 0040h to 083fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ra m are located in the direct area; inst ructions with shorten operations are available against such an area. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 2048 bytes 083f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h 1000 h flash: program memory flash 61440 bytes ffb0 h vector table for interrupts (16 bytes) ffbf h ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h
page 10 2. operational description 2.2 system clock controller TMP86FS49BFG the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an exte rnal oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. example :clears ram to ?00h?. (TMP86FS49BFG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 07ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers
page 11 TMP86FS49BFG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock
page 12 2. operational description 2.2 system clock controller TMP86FS49BFG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 and tbtcr, that is shown in figure 2-4. as reset and stop mode star ted/canceled, the prescaler and the divider are cleared to ?0?. figure 2-4 configurat ion of timing generator multi- plexer high-frequency clock fc low-frequency clock fs divider sysck fc/4 fc or fs machine cycle counters main system clock generator 1 2 1 4 3 2 8 7 10 9 12 11 14 13 16 15 dv7ck multiplexer warm-up controller watchdog timer a s b y s b0 a0 y0 b1 a1 y1 5 6 17 18 19 20 21 timer counter, serial interface, time-base-timer, divider output, etc. (peripheral functions)
page 13 TMP86FS49BFG note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are cont rolled by the system cont rol registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86FS49BFG is placed in this mode after reset. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s]
page 14 2. operational description 2.2 system clock controller TMP86FS49BFG (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 = "1", and idle1 mode is released to normal1 mode by an interrupt request from the on-chip peri pherals or external interrupt inputs. when the imf (interrupt master enable flag) is ?1? (interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to nor mal after the interrupt service is completed. when the imf is ?0? (interrupt disable), the execution will resume with the instruction which follows the idle1 mode start instruction. (3) idle0 mode in this mode, all the circuit, except oscillator an d the timer-base-timer, stops operation. this mode is enabled by syscr2 = "1". when idle0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to al l peripheral circuits. when returned from idle0 mode, the cpu rest arts operating, entering normal1 mode back again. idle0 mode is entered and returned regardless of how tbtcr is set. when imf = ?1?, ef7 (tbt interrupt individu al enable flag) = ?1?, and tb tcr = ?1?, interrupt pro- cessing is performed. when idle0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to normal1 mode. 2.2.3.2 dual-clock mode both the high-frequency and low-frequency oscillatio n circuits are used in th is mode. p21 (xtin) and p22 (xtout) pins cannot be used as input/output ports. the main system clock is obtained from the high-frequency clock in normal2 and idle2 modes, and is obtained from the low-frequency clock in slow and sleep modes. th e machine cycle time is 4/fc [s] in the normal2 and idle2 modes, and 4/fs [s] (122 s at fs = 32.768 khz) in the slow and sleep modes. the tlcs-870/c is placed in the signal-clock mode during reset. to use the dual-clock mode, the low- frequency oscillator should be turned on at the start of a program. (1) normal2 mode in this mode, the cpu core operates with the high-frequency clock. on-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) slow2 mode in this mode, the cpu core operates with the lo w-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. as the syscr2 becomes "1", the hard- ware changes into slow2 mode. as the syscr2 becomes ?0?, the hardware changes into normal2 mode. as the syscr2 beco mes ?0?, the hardware changes into slow1 mode. do not clear syscr2 to ?0? during slow2 mode. (3) slow1 mode this mode can be used to reduce power-consu mption by turning off oscillation of the high-fre- quency clock. the cpu core and on-chip peri pherals operate using th e low-frequency clock.
page 15 TMP86FS49BFG switching back and forth between slow1 and slow2 modes are performed by syscr2. in slow1 and sleep modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (4) idle2 mode in this mode, the internal oscillation circuit remain active. the cpu and the watchdog timer are halted; however, on-chip peripherals remain activ e (operate using the high-frequency clock and/or the low-frequency clock). starting and releasing of idle2 mode are the same as for idle1 mode, except that operation re turns to normal2 mode. (5) sleep1 mode in this mode, the internal oscillation circuit of the low-frequency clock remains active. the cpu, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how- ever, on-chip peripherals remain active (operate us ing the low-frequency clock). starting and releas- ing of sleep mode are the same as for idle1 mo de, except that operation returns to slow1 mode. in slow1 and sleep1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (6) sleep2 mode the sleep2 mode is the idle mode corresponding to the slow2 mode. the status under the sleep2 mode is same as that under the sleep1 mo de, except for the oscilla tion circuit of the high- frequency clock. (7) sleep0 mode in this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. this mode is enabled by setting ?1? on bit syscr2. when sleep0 mode starts, the cp u stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to al l peripheral circuits. when returned from sleep0 mode, the cpu restarts operating, entering slow1 mode back again. sleep0 mode is entered and returned re gardless of how tbtcr is set. when imf = ?1?, ef7 (tbt interrupt individual enable flag ) = ?1?, and tbtcr = ?1?, interrupt pro- cessing is performed. when sleep0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to slow1 mode. 2.2.3.3 stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop mode. stop mode is started by the syst em control register 1 (syscr1), an d stop mode is released by a inputting (either level-sensitive or edge-sens itive can be programmably selected) to the stop pin. after the warm-up period is completed, the execution resumes with the instruction which follows the stop mode start instruction.
page 16 2. operational description 2.2 system clock controller TMP86FS49BFG note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by fa lling edge of tbtcr setting. figure 2-6 operating mode transition diagram table 2-1 operating mode and conditions operating mode oscillator cpu core tbt other peripherals machine cycle time high frequency low frequency single clock reset oscillation stop reset reset reset 4/fc [s] normal1 operate operate operate idle1 halt idle0 halt stop stop halt ? dual clock normal2 oscillation oscillation operate with high frequency operate operate 4/fc [s] idle2 halt slow2 operate with low frequency 4/fs [s] sleep2 halt slow1 stop operate with low frequency sleep1 halt sleep0 halt stop stop halt ? note 2 syscr2 = "1" stop pin input stop pin input stop pin input interrupt interrupt syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "0" syscr1 = "1" syscr1 = "1" syscr1 = "1" syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" reset release normal1 mode idle0 mode (a) single-clock mode idle1 mode normal2 mode idle2 mode syscr2 = "1" slow2 mode sleep2 mode slow1 mode sleep1 mode sleep0 mode reset (b) dual-clock mode stop syscr2 = "1" note 2
page 17 TMP86FS49BFG note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator, *; don?t care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr. note 6: when idle1/2 or sleep1/2 mode is rel eased, idle is automatically cleared to ?0?. note 7: when idle0 or sleep0 mode is released, tghalt is automatically cleared to ?0?. note 8: before setting tghalt to ?1?, be sure to stop peripheral s. if peripherals are not stopped, the interrupt latch of periph erals may be set after idle0 or sleep0 mode is released. system control register 1 syscr176543210 (0038h) stop relm retm outen wut (initial value: 0000 00**) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release r/w retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode r/w outen port output during stop mode 0: high impedance 1: output kept r/w wut warm-up time at releasing stop mode return to normal mode return to slow mode r/w 00 01 10 11 3 x 2 16 /fc 2 16 /fc 3 x 2 14 /fc 2 14 /fc 3 x 2 13 /fs 2 13 /fs 3 x 2 6 /fs 2 6 /fs system control register 2 syscr2 (0039h) 76543210 xen xten sysck idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/main system clock moni- tor (read) 0: high-frequency clock (normal1/normal2/idle1/idle2) 1: low-frequency clock (slow1/slow2/sleep1/sleep2) idle cpu and watchdog timer control (idle1/2 and sleep1/2 modes) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1/2 and sleep1/2 modes) r/w tghalt tg control (idle0 and sleep0 modes) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg. (start idle0 and sleep0 modes)
page 18 2. operational description 2.2 system clock controller TMP86FS49BFG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop3 to stop0) which is controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 to ?1?. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers, the program status wo rd and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of th e timing generator are cleared to ?0?. 4. the program counter holds the address 2 ahead of th e instruction (e.g., [set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the syscr1. do not use any key-on wakeup input (stop3 to stop0) for releas- ing stop mode in edge-sensitive mode. note 1: the stop mode can be released by either th e stop or key-on wakeup pin (stop3 to stop0). however, because the stop pin is different from the key-on wakeup and can not inhibit the release input, the stop pin must be used for releasing stop mode. note 2: during stop period (from start of stop mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to ?1? and interrupts may be accepted immediately after stop mode is released. before starting stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is rel eased, clear unnecessary interrupt latches. (1) level-sensitive release mode (relm = ?1?) in this mode, stop mode is released by setting the stop pin high or setting the stop3 to stop0 pin input which is enabled by stopcr. this mo de is used for capacitor backup when the main power supply is cut off and long term battery backup. even if an instruction for starting stop mode is executed while stop pin input is high or stop3 to stop0 input is low, stop mode does not start but instead the warm-up sequence starts immedi- ately. thus, to start stop mode in the level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low or stop3 to stop0 input is high. the following two methods can be used for confirmation. 1. testing a port. 2. using an external interrupt input int5 ( int5 is a falling edge-sensitive input). example 1 :starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2prd). 0 ; wait until the stop pin input goes low level jrs f, sstoph di ; imf 0 set (syscr1). 7 ; starts stop mode
page 19 TMP86FS49BFG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop3 to stop0 pin input for releasing stop mode in edge-sensitive release mode. figure 2-8 edge-sensitive release mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin
page 20 2. operational description 2.2 system clock controller TMP86FS49BFG stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 in accordance with the resonator characteristics. 3. when the warm-up time has elapsed, normal operation resumes with the instruction follow- ing the stop mode start instruction. note 1: when the stop mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". note 2: stop mode can also be released by inputting low level on the reset pin, which immediately performs the normal reset operation. note 3: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be ?h? level, rising together with the power supply voltage. in this case, if an external time const ant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply vo ltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). note 1: the warm-up time is obtained by dividing the ba sic clock by the divider. therefore, the warm-up time may include a certain amount of error if ther e is any fluctuation of the oscillation frequency when stop mode is released. thus, the warm -up time must be considered as an approximate value. table 2-2 warm-up time example (at fc = 16.0 mhz, fs = 32.768 khz) wut warm-up time [ms] return to normal mode return to slow mode 00 01 10 11 12.288 4.096 3.072 1.024 750 250 5.85 1.95
page 21 TMP86FS49BFG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock
page 22 2. operational description 2.2 system clock controller TMP86FS49BFG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction
page 23 TMP86FS49BFG ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual inte rrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sl eep1/2 modes, set syscr2 to ?1?. ? release the idle1 /2 and sleep1/2 modes idle1/2 and sleep1/2 modes include a normal release mode and an interrupt release mode. these modes are selected by interrupt master en able flag (imf). after releasing idle1/2 and sleep1/2 modes, the syscr2 is automa tically cleared to ?0? and the operation mode is returned to the mode preced ing idle1/2 and sleep1/2 modes. idle1/2 and sleep1/2 modes can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. (1) normal release mode (imf = ?0?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (ef). after the interrupt is ge nerated, the program operation is resumed from the instruction following the idle1/2 and sleep1/2 mo des start instruction. normally, the interrupt latches (il) of the interrupt source used for releas ing must be cleared to ?0? by load instructions. (2) interrupt release mode (imf = ?1?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (ef) and the interrupt processi ng is started. after the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts idle1/2 and sleep1/2 modes. note: when a watchdog timer interrupts is generated immediately before idle1/2 and sleep1/2 modes are started, the watchdog timer interrupt will be processed but idle1/2 and sleep1/2 modes will not be started.
page 24 2. operational description 2.2 system clock controller TMP86FS49BFG figure 2-11 idle1/2 and sleep1/2 modes start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release
page 25 TMP86FS49BFG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr = "1" interrupt processing imf = "1" yes tbt interrupt enable no no no no stopping peripherals by instruction yes starting idle0, sleep0 modes by instruction execution of the instruction which follows the idle0, sleep0 modes start instruction
page 26 2. operational description 2.2 system clock controller TMP86FS49BFG ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 modes, set syscr2 to ?1?. ? release the idle0 and sleep0 modes idle0 and sleep0 modes include a normal re lease mode and an interrupt release mode. these modes are selected by inte rrupt master flag (imf), the i ndividual interrupt enable flag of tbt and tbtcr. after releasing idle0 and sleep0 modes, the syscr2 is automatically cleared to ?0? and the operatio n mode is returned to the mode preceding idle0 and sleep0 modes. before starting the idle0 or sleep0 mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. idle0 and sleep0 modes can also be re leased by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. note: idle0 and sleep0 modes start/release wi thout reference to tbtcr setting. (1) normal release mode (imf ? ef7 ? tbtcr = ?0?) idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr. after the falling edge is detect ed, the program operation is resumed from the instruction following the idle0 and sleep0 modes start instruction. before starting the idle0 or sleep0 mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. (2) interrupt release mode (imf ? ef7 ? tbtcr = ?1?) idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr and inttbt interrupt processing is started. note 1: because returning from idle0, sleep0 to normal1, slow1 is executed by the asynchro- nous internal clock, the period of idle0, sleep0 mode might be the shorter than the period set- ting by tbtcr. note 2: when a watchdog timer interrupt is generat ed immediately before idle0/sleep0 mode is started, the watchdog timer interrupt will be processed but idle0/sleep0 mode will not be started.
page 27 TMP86FS49BFG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release
page 28 2. operational description 2.2 system clock controller TMP86FS49BFG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 to switch the main system clock to the low-frequency clock for slow2 mode. next, clear syscr2 to turn off high-frequency oscillation. note: the high-frequency clock can be co ntinued oscillation in order to return to normal2 mode from slow mode quickly. always turn off oscillat ion of high-frequency clock when switching from slow mode to stop mode. example 1 :switching from normal2 mode to slow1 mode. set (syscr2). 5 ; syscr2 1 (switches the main system clock to the low-frequency clock for slow2) clr (syscr2). 7 ; syscr2 0 (turns off high-frequency oscillation) example 2 :switching to the slow1 mode after low-frequency clock has stabilized. set (syscr2). 6 ; syscr2 1 ld (tc5cr), 43h ; sets mode for tc6, 5 (16-bit mode, fs for source) ld (tc6cr), 05h ; sets warming-up counter mode ldw (ttreg5), 8000h ; sets warm-up time (depend on oscillator accompanied) di ; imf 0 set (eire). 2 ; enables inttc6 ei ; imf 1 set (tc6cr). 3 ; starts tc6, 5 : pinttc6: clr (tc6cr). 3 ; stops tc6, 5 set (syscr2). 5 ; syscr2 1 (switches the main system cl ock to the low-frequency clock) clr (syscr2). 7 ; syscr2 0 (turns off high-frequency oscillation) reti : vinttc6: dw pinttc6 ; inttc6 vector table
page 29 TMP86FS49BFG (2) switching from slow1 mode to normal2 mode note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. first, set syscr2 to turn on the high-fre quency oscillation. when time for stabilization (warm up) has been taken by the timer/counter (tc6,tc5), clear syscr2 to switch the main system clock to the high-frequency clock. slow mode can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. example :switching from the slow1 mode to the normal2 mode (fc = 16 mhz, warm-up time is 4.0 ms). set (syscr2). 7 ; syscr2 1 (starts high-frequency oscillation) ld (tc5cr), 63h ; sets mode for tc6, 5 (16-bit mode, fc for source) ld (tc6cr), 05h ; sets warming-up counter mode ld (ttreg6), 0f8h ; sets warm-up time di ; imf 0 set (eire). 2 ; enables inttc6 ei ; imf 1 set (tc6cr). 3 ; starts tc6, 5 : pinttc6: clr (tc6cr). 3 ; stops tc6, 5 clr (syscr2). 5 ; syscr2 0 (switches the main system clock to the high-frequency clock) reti : vinttc6: dw pinttc6 ; inttc6 vector table high-frequency clock low-frequency clock main system clock sysck
page 30 2. operational description 2.2 system clock controller TMP86FS49BFG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode
page 31 TMP86FS49BFG 2.3 reset circuit the TMP86FS49BFG has four types of re set generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system cloc k reset. of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction re set. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5 s at 16.0 mhz) when power is turned on. table 2-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset
page 32 2. operational description 2.3 reset circuit TMP86FS49BFG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 is set to ?1 ?), dbr or the sfr area, ad dress trap reset will be generated. the reset time is maximum 24/fc[s] (1.5 s at 16.0 mhz). note:the operating mode under address tr apped is alternative of reset or interrupt. the address trap area is alter- native. note 1: address ?a? is in the sfr, dbr or on-chip ram (wdtcr1 = ?1?) space. note 2: during reset release, reset vector ?r? is read out, and an instruction at address ?r? is fetched and decoded. figure 2-16 addr ess trap reset 2.3.3 watchdog timer reset refer to section ?watchdog timer?. 2.3.4 system clock reset if the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the cpu. (the oscillation is continued without stopping.) - in case of clearing syscr2 an d syscr2 simultaneously to ? 0 ? . - in case of clearing syscr2 to ? 0 ? , when the syscr2 is ? 0 ? . - in case of clearing syscr2 to ? 0 ? , when the syscr2 is ? 1 ? . the reset time is maximum 24/fc (1.5 s at 16.0 mhz). instruction at address r 16/fc [s] maximum 24/fc [s] instruction execution internal reset jp a reset release address trap is occurred 4/fc to 12/fc [s]
page 33 TMP86FS49BFG
page 34 2. operational description 2.3 reset circuit TMP86FS49BFG
page 35 TMP86FS49BFG 3. interrupt control circuit the TMP86FS49BFG has a total of 24 interrupt sources excl uding reset. interrupts can be nested with priorities. four of the internal interrupt sources ar e non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. note 1: to use the address trap interrupt (intatrap), clear wdtcr1 to ?0? (it is set for the ?reset request? after reset is cancelled). for details , see ?address trap?. note 2: to use the watchdog timer interrupt (intwdt), clear wdtcr1 to "0" (it is set for the "reset request" after reset is released). for details, see "watchdog timer". note 3: if an intadc interrupt request is generated while an interrupt with priority lower than the interrupt latch il15 (intadc ) is being accepted, the intadc interrupt latch may be cleared wi thout the intadc interrupt being processed. for details, refer to the corresponding notes in the chapter on the ad converter. 3.1 interrupt latches (il23 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. interrupt factors enable condition interrupt latch vector address priority internal/external (reset) non-maskable ? fffe 1 internal intswi (software interrupt) non-maskable ? fffc 2 internal intundef (executed the undefined instruction interrupt) non-maskable ? fffc 2 internal intatrap (address trap interrupt) non-maskable il2 fffa 2 internal intwdt (watchdog timer interrupt) non-maskable il3 fff8 2 external int0 imf? ef4 = 1, int0en = 1 il4 fff6 5 internal inttc1 imf? ef5 = 1 il5 fff4 6 external int1 imf? ef6 = 1 il6 fff2 7 internal inttbt imf? ef7 = 1 il7 fff0 8 external int2 imf? ef8 = 1 il8 ffee 9 internal inttc4 imf? ef9 = 1 il9 ffec 10 internal inttc3 imf? ef10 = 1 il10 ffea 11 internal intsbi imf? ef11 = 1 il11 ffe8 12 external int3 imf? ef12 = 1 il12 ffe6 13 internal intsio1 imf? ef13 = 1 il13 ffe4 14 internal intsio2 imf? ef14 = 1 il14 ffe2 15 internal intadc imf? ef15 = 1 il15 ffe0 16 internal intrxd1 imf? ef16 = 1 il16 ffbe 17 internal inttxd1 imf? ef17 = 1 il17 ffbc 18 internal inttc6 imf? ef18 = 1 il18 ffba 19 internal inttc5 imf? ef19 = 1 il19 ffb8 20 internal intrxd2 imf? ef20 = 1 il20 ffb6 21 internal inttxd2 imf? ef21 = 1 il21 ffb4 22 internal inttc2 imf? ef22 = 1 il22 ffb2 23 external int5 imf? ef23 = 1 il23 ffb0 24
page 36 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FS49BFG the interrupt latches are located on address 002eh, 003ch and 003dh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 sh ould not be cleared to "0" by software. for clearing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify-write instructions such as bit manipulation or operation instru ctions are used, interrupt re quest would be cleared inade- quately if interrupt is requested while such instructions are executed. interrupt latches are not set to ?1? by an instruction. since interrupt latches can be read, the status fo r interrupt requests can be monitored by software. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 002ch, 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. example 1 :clears interrupt latches di ; imf 0 ldw (ill), 111010000011 1111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latchess ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset
page 37 TMP86FS49BFG 3.2.2 individual interrupt enable flags (ef23 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef23 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei();
page 38 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FS49BFG note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) (initial value: 00000000) ile (002eh) 76543210 il23 il22 il21 il20 il19 il18 il17 il16 ile (002eh) il23 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) (initial value: 00000000) eire (002ch) 76543210 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 eire (002ch) ef23 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts
page 39 TMP86FS49BFG 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruct ion. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address entry address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program figure 3-2 vector table address,entry address a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff0h fff1h
page 40 3. interrupt control circuit 3.3 interrupt sequence TMP86FS49BFG a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5
page 41 TMP86FS49BFG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task
page 42 3. interrupt control circuit 3.4 software interrupt (intsw) TMP86FS49BFG interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary pro- cess is broken and intatrap interrupt pro cess starts, soon afte r it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address
page 43 TMP86FS49BFG 3.7 external interrupts the TMP86FS49BFG has 5 external interrupt inputs. thes e inputs are equipped with digital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int3. the int0 /p00 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p00 pin function selection are performed by the external interrupt control register (eintcr). note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "si g- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin enable conditions release edge digital noise reject int0 int0 imf ? ef4 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int1 int1 imf ? ef6 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ? ef8 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int3 int3 imf ? ef12 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int5 int5 imf ? ef23 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals.
page 44 3. interrupt control circuit 3.7 external interrupts TMP86FS49BFG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. external interrupt control register eintcr76543210 (0037h) int1nc int0en - - int3es int2es int1es (initial value: 00** 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p00/ int0 pin configuration 0: p00 input/output port 1: int0 pin (port p00 should be set to an input mode) r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w
page 45 TMP86FS49BFG 4. special function register (sfr) the TMP86FS49BFG adopts the memory mapped i/o system , and all peripheral contro l and data transfers are performed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP86FS49BFG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h p5dr 0006h p6dr 0007h p7dr 0008h p0outcr 0009h p1cr 000ah p4outcr 000bh p0prd - 000ch p2prd - 000dh p3prd - 000eh p4prd - 000fh p5prd - 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h ttreg3 0015h ttreg4 0016h ttreg5 0017h ttreg6 0018h pwreg3 0019h pwreg4 001ah pwreg5 001bh pwreg6 001ch adccr1 001dh adccr2 001eh adcdr2 - 001fh adcdr1 - 0020h sio1cr 0021h sio1sr - 0022h sio1rdb sio1tdb 0023h tc2cr 0024h tc2drl 0025h tc2drh
page 46 4. special function register (sfr) 4.1 sfr TMP86FS49BFG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h tc1cr 0027h tc3cr 0028h tc4cr 0029h tc5cr 002ah tc6cr 002bh sio2rdb sio2tdb 002ch eire 002dh reserved 002eh ile 002fh reserved 0030h reserved 0031h sio2cr 0032h sio2sr - 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh reserved 003fh psw address read write
page 47 TMP86FS49BFG 4.2 dbr address read write 0f80h reserved 0f81h reserved 0f82h reserved 0f83h reserved 0f84h reserved 0f85h reserved 0f86h reserved 0f87h reserved 0f88h reserved 0f89h reserved 0f8ah reserved 0f8bh reserved 0f8ch reserved 0f8dh reserved 0f8eh reserved 0f8fh reserved 0f90h sbisra sbicra 0f91h sbidbr 0f92h - i2car 0f93h sbisrb sbicrb 0f94h reserved 0f95h uart1sr uart1cr1 0f96h - uart1cr2 0f97h rd1buf td1buf 0f98h uart2sr uart2cr1 0f99h - uart2cr2 0f9ah rd2buf td2buf 0f9bh p6cr1 0f9ch p6cr2 0f9dh p7cr1 0f9eh p7cr2 0f9fh - stopcr address read write 0fa0h reserved : : : : 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved
page 48 4. special function register (sfr) 4.2 dbr TMP86FS49BFG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). address read write 0fe0h reserved 0fe1h reserved 0fe2h reserved 0fe3h reserved 0fe4h reserved 0fe5h reserved 0fe6h reserved 0fe7h reserved 0fe8h reserved 0fe9h reserved 0feah reserved 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h reserved 0ff1h reserved 0ff2h reserved 0ff3h reserved 0ff4h reserved 0ff5h reserved 0ff6h reserved 0ff7h reserved 0ff8h reserved 0ff9h reserved 0ffah reserved 0ffbh reserved 0ffch reserved 0ffdh reserved 0ffeh reserved 0fffh flscr
page 49 TMP86FS49BFG 5. i/o ports the TMP86FS49BFG has 8 parallel input/output ports (56 pins) as follows. each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. output data changes in the s2 state of the write cycle du ring execution of the instruct ion which writes to an i/o port. note: the positions of the read and write c ycles may vary, depending on the instruction. figure 5-1 input/output timing (example) primary function secondary functions port p0 8-bit i/o port external interrupt, serial prom mode cotrol input, serial interface input/output, uart input/output. port p1 8-bit i/o port external interrupt, ti mer counter input/output, divider output. port p2 3-bit i/o port low-frequency resonator connections, external interrupt input, stop mode release signal input. port p3 8-bit i/o port port p4 8-bit i/o port serial interface input/output and uart input/output. port p5 5-bit i/o port serial bus interface input/output. port p6 8-bit i/o port analog input and key-on wakeup input. port p7 8-bit i/o port analog input. data output data input new old example: ld a, (x) fetch cycle read cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle input strobe (a) input timing example: ld (x), a fetch cycle write cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (b) output timing instruction execution cycle output strobe
page 50 5. i/o ports 5.1 port p0 (p07 to p00) TMP86FS49BFG 5.1 port p0 (p07 to p00) port p0 is an 8-bit input/output port. port p0 is also used as an external interrupt input, serial prom mode control input, a serial interface input/output and an uart input/output. when used as an input port, an exte rnal interrupt input , a serial interface input/output and an uart input/output, the corresponding output latch (p0dr) should be set to "1". during reset, the p0dr is initialized to "1", and the p0outcr is initialized to "0". it can be selected whether output circ uit of p0 port is a c-mos output or a sink open drain individually, by setting p0outcr. when a corresponding bit of p0outcr is "0", the output circuit is selected to a sink open drain and when a corresponding bit of p0outcr is "1", the output circuit is selected to a c-mos output. when used as an input port, an external interrupt input , a serial interface input and an uart input, the correspond- ing output control (p0outcr) should be set to "0" after p0dr is set to "1". p0 port output latch (p0dr) and p0 port terminal input (p0prd) are located on their respective address. when read the output latch data, the p0dr should be read . when read the terminal input data, the p0prd register should be read. note: i = 7 to 0 figure 5-2 port 0 and p0outcr table 5-1 register programming for multi-function ports (p07 to p00) function programmed value p0dr p0outcr port input, external interrupt input, serial inter- face input or uart input, serial prom mode cotrol input ?1? ?0? port ?0? output ?0? programming for each applica- tions port ?1? output, serial interface output or uart output ?1? data output (p0dr) control output stop outen p0outcri dq p0i p0outcri input data input (p0prd) output latch read (p0dr) control input dq output latch
page 51 TMP86FS49BFG p0dr (0000h) r/w 76543210 p07 int2 p06 sck1 p05 so1 p04 si1 p03 int1 p02 txd1 p01 rxd1 boot p00 int0 (initial value: 1111 1111) p0outcr (0008h) (initial value: 0000 0000) p0outcr port p0 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p0prd (000bh) read only p07 p06 p05 p04 p03 p02 p01 p00
page 52 5. i/o ports 5.2 port p1 (p17 to p10) TMP86FS49BFG 5.2 port p1 (p17 to p10) port p1 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p1 is also used as a timer/counter input/output, an external interrupt input and a divider output. input/output mode is specified by the p1 control register (p1cr). during reset, the p1cr is initialized to "0" and port p1 becomes an input mode. and the p1dr is initialized to "0". when used as an input port, a timer/counter input and an external interrupt input, the corresponding bit of p1cr should be set to "0". when used as an output port, the corresponding bit of p1cr should be set to "1". when used as a timer/counter output and a divider output, p1dr is set to "1" beforehand and the corresponding bit of p1cr should be set to "1". when p1cr is "1", the content of the correspon ding output latch is read by reading p1dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. note: i = 7 to 0 figure 5-3 port 1 and p1cr note: the port set to an input mode reads the terminal input data. therefore, when the input and output modes are used together, the content of the output latch which is s pecified as input mode might be changed by executing a bit manipulation instruction. table 5-2 register programming for multi-function ports function programmed value p1dr p1cr port input, timer/counter input or external interrupt input *?0? port ?0? output ?0? ?1? port ?1? output, a timer output or a divider output ?1? ?1? p1i dq dq stop outen p1cri p1cri input data input (p1dr) data output (p1dr) control output control input output latch
page 53 TMP86FS49BFG p1dr (0001h) r/w 76543210 p17 tc6 pwm6 pdo6 ppg6 p16 tc5 pwm5 pdo5 p15 tc2 int3 p14 tc4 pwm4 pdo4 ppg4 p13 tc3 pwm3 pdo3 p12 ppg p11 dvo p10 tc1 (initial value: 0000 0000) p1cr (0009h) 76543210 (initial value: 0000 0000) p1cr i/o control for port p1 (specified for each bit) 0: input mode 1: output mode r/w
page 54 5. i/o ports 5.3 port p2 (p22 to p20) TMP86FS49BFG 5.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interr upt, a stop mode release signal input, and low-frequency crys tal oscillator con- nection pins. when used as an input port or a secondary function pins, respective output latch (p2dr) should be set to ?1?. during reset, the p2dr is initialized to ?1?. a low-frequency crystal osci llator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual- clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an exte rnal interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the in terrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal i nput (p2prd) are located on their respective address. when read the output latch data, the p2dr should be r ead and when read the termin al input data, the p2prd reg- ister should be read. if a read instruction is execute d for port p2, read data of bits 7 to 3 are unstable. figure 5-4 port 2 note: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. p2dr (0002h) r/w 76543210 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (000ch) read only p22 p21 p20 output latch osc. enable output latch dq p20 (int5, stop) dq output latch dq p21 (xtin) p22 (xtout) data input (p20prd) data input (p20) data output (p20) contorl input data input (p21prd) output latch read (p21) data output (p21) data input (p22prd) output latch read (p22) data output (p22) stop outen xten fs
page 55 TMP86FS49BFG 5.4 port p3 (p37 to p 30) (large c urrent port) port p3 is an 8-bit input/output port. when used as an input port, the corresponding output latch (p3dr) should be set to "1". during reset, the p3dr is initialized to "1". p3 port output latch (p3dr) and p3 port terminal input (p3prd) are located on their respective address. when read the output latch data, the p3dr should be read . when read the terminal input data, the p3prd register should be read. note: i = 7 to 0 figure 5-5 port 3 p3dr (0003h) 76543210 p37 p36 p35 p34 p33 p32 p31 p30 (initial value: 1111 1111) r/w p3prd (000dh) read only p37 p36 p35 p34 p33 p32 p31 p30 data output (p3dr) stop outen dq p3i data input (p3prd) output latch read (p3dr)
page 56 5. i/o ports 5.5 port p4 (p47 to p40) TMP86FS49BFG 5.5 port p4 (p47 to p40) port p4 is an 8-bit input/output port. port p4 is also used as a serial inte rface input/output and an uart input/output. when used as an input port, a serial interface input/out put and an uart input/output, the corresponding output latch (p4dr) should be set to "1". during reset, the p4dr is initialized to "1", and the p4outcr is initialized to "0". it can be selected whether output circ uit of p4 port is a c-mos output or a sink open drain individually, by setting p4outcr. when a corresponding bit of p4outcr is "0", the output circuit is selected to a sink open drain and when a corresponding bit of p4outcr is "1", the output circuit is selected to a c-mos output. when used as an input port, a serial interface inpu t and an uart input, the corresponding output control (p4outcr) should be set to "0" after p4dr is set to "1". p4 port output latch (p4dr) and p4 port terminal input (p4prd) are located on their respective address. when read the output latch data, the p4dr should be read . when read the terminal input data, the p4prd register should be read. note: i = 7 to 0 figure 5-6 port 4 table 5-3 register programming for multi-function ports (p47 to p40) function programmed value p4dr p4outcr port input uart input or serial interface input ?1? ?0? port ?0? output ?0? programming for each applica- tions port ?1? output uart output or serial interface output ?1? data output (p4dr) control output stop outen p4outcri dq p4i p4outcri input data input (p4prd) output latch read (p4dr) control input dq output latch
page 57 TMP86FS49BFG p4dr (0004h) r/w 76543210 p47 p46 sck2 p45 so2 p44 si2 p43 p42 txd2 p41 rxd2 p40 (initial value: 1111 1111) p4outcr (000ah) (initial value: 0000 0000) p4outcr port p4 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p4prd (000eh) read only p47 p46 p45 p44 p43 p42 p41 p40
page 58 5. i/o ports 5.6 port p5 (p54 to p50) (large current port) TMP86FS49BFG 5.6 port p5 (p54 to p 50) (large c urrent port) port p5 is an 5-bit input/output port. port p5 is also used as an i 2 c bus input/output. when used as an input port and i 2 c bus input/output, the corresponding output latch (p5dr) should be set to "1". during reset, the p5dr is initialized to "1". p5 port output latch (p5dr) and p5 port terminal input (p5prd) are located on their respective address. when read the output latch data, the p5dr should be read . when read the terminal input data, the p5prd register should be read. if a read instruction is execu ted for port p5, read data of bit 7 to 5 are unstable. note: i = 4 to 0 figure 5-7 port 5 p5dr (0005h) r/w 76543210 p54p53p52p51 sda p50 scl (initial value: ***1 1111) p5prd (000fh) read only p54p53p52p51p50 data output (p5dr) control output stop outen dq p5i data input (p5prd) output latch read (p5dr) control input output latch
page 59 TMP86FS49BFG 5.7 port p6 (p67 to p60) port p6 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p6 is also used as an analog input and key-on wakeup input. input/output mode is specified by the p6 control register (p6cr1) and p6 input control register (p6cr2). during reset, the p6cr1 is initialized to "0" the p6cr2 is initialized to "1" and port p6 becomes an input mode. and the p6dr is initialized to "0". when used as an output port, the corresponding bit of p6cr1 should be set to "1". when used as an input port , the corresponding bit of p6cr1 should be set to "0" and then, the corresponding bit of p6cr2 should be set to "1". when used as a key-on wakeup input , the corresponding bi t of p6cr1 should be set to "0" and then, the corre- sponding bit of stopken should be set to "1". when used as an analog input, the corresponding bit of p6cr1 should be set to "0" and then, the corresponding bit of p6cr2 should be set to "0". when p6cr1 is "1", the content of the corres ponding output latch is read by reading p6dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. table 5-4 register programming for multi-function ports function programmed value p6dr p6cr1 p6cr2 stopken port input * ?0? ?1? * key-on wakeup input * "0" * "1" analog input * ?0? ?0? * port ?0? output ?0? ?1? * * port ?1? output ?1? ?1? * * table 5-5 values read from p6dr and register programming conditions values read from p6dr p6cr1 p6cr2 ?0? ?0? ?0? ?0? ?1? terminal input data ?1? ?0? output latch contents ?1?
page 60 5. i/o ports 5.7 port p6 (p67 to p60) TMP86FS49BFG note 1: i = 3 to 0, j = 7 to 4, k = 3 to 0 note 2: stop is bit7 in syscr1. note 3: sain is ad input select signal. note 4: stopken is input select signal in a key-on wakeup. figure 5-8 port 6, p6cr1 and p6cr2 p6i dq dq p6cr2i p6cr2i input p6cr1i p6cr1i input data input (p6dri) data output (p6dri) stop outten analog input ainds sain dq control input p6j dq dq p6cr2j p6cr2j input p6cr1j p6cr1j input data output (p6drj) stop outten analog input ainds stopken key-on wakeup dq data input (p6drj) a) p63 to p60 sain b) p67 to p64
page 61 TMP86FS49BFG note 1: the port placed in input mode reads the pin input stat e. therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bi t manipulation instruction. note 2: when used as an analog inport, be sure to clear the corresponding bit of p6cr2 to disable the port input. note 3: do not set the output mode (p6cr1 = ?1?) for the pin used as an analog input pin. note 4: pins not used for analog input can be used as i/o ports. during ad conversion, output instructions should not be execute d to keep a precision. in addition, a variabl e signal should not be input to a port ad jacent to the analog input during ad con- version. p6dr (0006h) r/w 76543210 p67 ain7 stop3 p66 ain6 stop2 p65 ain5 stop1 p64 ain4 stop0 p63 ain3 p62 ain2 p61 ain1 p60 ain0 (initial value: 0000 0000) p6cr1 (0f9bh) 76543210 (initial value: 0000 0000) p6cr1 i/o control for port p6 (specified for each bit) 0: input mode 1: output mode r/w p6cr2 (0f9ch) 76543210 (initial value: 1111 1111) p6cr2 p6 port input control (specified for each bit) 0: analog input 1: port input r/w
page 62 5. i/o ports 5.8 port p7 (p77 to p70) TMP86FS49BFG 5.8 port p7 (p77 to p70) port p7 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p7 is also used as an analog input. input/output mode is specified by the p7 control register (p7cr1) and p7 input control register (p7cr2). during reset, the p7cr1 is initialized to "0" the p7cr2 is initialized to "1" and port p7 becomes an input mode. and the p7dr is initialized to "0". when used as an output port, the corresponding bit of p7cr1 should be set to "1". when used as an input port, the corresponding bit of p7 cr1 should be set to "0" and then, the corresponding bit of p7cr2 should be set to "1". when used as an analog input, the corresponding bit of p7cr1 should be set to "0" and then, the corresponding bit of p7cr2 should be set to "0". when p7cr1 is "1", the content of the corres ponding output latch is read by reading p7dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. table 5-6 register programming for multi-function ports function programmed value p7dr p7cr1 p7cr2 port input * ?0? ?1? analog input * ?0? ?0? port ?0? output ?0? ?1? * port ?1? output ?1? ?1? * table 5-7 values read from p7dr and register programming conditions values read from p7dr p7cr1 p7cr2 ?0? ?0? ?0? ?0? ?1? terminal input data ?1? ?0? output latch contents ?1?
page 63 TMP86FS49BFG note 1: i = 7 to 0 note 2: stop is bit7 in syscr1. note 3: sain is ad input select signal. figure 5-9 port 7, p7cr1 and p7cr2 note 1: the port placed in input mode reads the pin input stat e. therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bi t manipulation instruction. note 2: when used as an analog inport, be sure to clear the corresponding bit of p7cr2 to disable the port input. note 3: do not set the output mode (p7cr1 = ?1?) for the pin used as an analog input pin. note 4: pins not used for analog input can be used as i/o ports. during ad conversion, output instructions should not be execute d to keep a precision. in addition, a variabl e signal should not be input to a port ad jacent to the analog input during ad con- version. p7dr (0007h) r/w 76543210 p77 ain15 p76 ain14 p75 ain13 p74 ain12 p73 ain11 p72 ain10 p71 ain9 p70 ain8 (initial value: 0000 0000) p7cr1 (0f9dh) 76543210 (initial value: 0000 0000) p7cr1 i/o control for port p7 (specified for each bit) 0: input mode 1: output mode r/w p7cr2 (0f9eh) 76543210 (initial value: 1111 1111) p7cr2 p7 port input control (specified for each bit) 0: analog input 1: port input r/w p7i dq dq p7cr2i p7cr2i input p7cr1i p7cr1i input data input (p7dri) data output (p7dri) stop outten analog input ainds sain dq control input
page 64 5. i/o ports 5.8 port p7 (p77 to p70) TMP86FS49BFG
page 65 TMP86FS49BFG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9
page 66 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FS49BFG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 is set to ?1? at this time, the reset request is generated and then internal hardware is initialized. when wdtcr1 is set to ?0?, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in th e stop mode including the warm-up or idle/sleep mode, and automatically restarts (continues counting) when the stop/idle/sleep mode is inactivated. note:the watchdog timer consists of an internal divider and a two-stage binary counter. when the clear code 4eh is written, only the binary counter is cleared, but not the internal divider . the minimum binary-counter overflow time, that depends on the timing at which the clear code (4eh) is written to the wdtcr2 register, may be 3/ 4 of the time set in wdtcr1. therefore, writ e the clear code using a cycle shorter than 3/4 of the time set to wdtcr1. example :setting the watchdog timer detection time to 2 21 /fc [s], and resetting the cpu malfunction detection ld (wdtcr2), 4eh : clears the binary counters. ld (wdtcr1), 00001101b : wdtt 10, wdtout 1 ld (wdtcr2), 4eh : clears the binary counters (always clears immediately before and after changing wdtt). within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters. within 3/4 of wdt detection time : : ld (wdtcr2), 4eh : clears the binary counters.
page 67 TMP86FS49BFG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?6.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 = 0. note 2: *: don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write the clear code 4eh using a cycle shor ter than 3/4 of the time set in wdtcr1. 6.2.2 watchdog timer enable setting wdtcr1 to ?1? enables the watc hdog timer. since wdtcr1 is initialized to ?1? during reset, the watchdog timer is enabled automatically after the reset release. watchdog timer control register 1 wdtcr1 (0034h) 76543210 (atas) (atout) wdten wdtt wdtout (initial value: **11 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal1/2 mode slow1/2 mode write only dv7ck = 0 dv7ck = 1 00 2 25 /fc 2 17 /fs 2 17 /fs 01 2 23 /fc 2 15 /fs 2 15 fs 10 2 21 fc 2 13 /fs 2 13 fs 11 2 19 /fc 2 11 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset request write only watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) d2h: enable assigning address trap area others: invalid write only
page 68 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FS49BFG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 to ?0?. 4. set wdtcr2 to the disable code (b1h). note:while the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. 6.2.4 watchdog time r interrupt (intwdt) when wdtcr1 is cleared to ?0?, a watchdog timer interrupt request (intwdt) is generated by the binary-counter overflow. a watchdog timer interrupt is the non-maskable interr upt which can be accepted regardless of the interrupt master flag (imf). when a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending. therefore, if watchdog timer interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate a watchdog timer interrupt, set the stack pointer before setting wdtcr1. example :disabling the watchdog timer di : imf 0 ld (wdtcr2), 04eh : clears the binary counter ldw (wdtcr1), 0b101h : wdten 0, wdtcr2 disable code table 6-1 watchdog timer detection time (example: fc = 16.0 mhz, fs = 32.768 khz) wdtt watchdog timer detection time[s] normal1/2 mode slow mode dv7ck = 0 dv7ck = 1 00 2.097 4 4 01 524.288 m 1 1 10 131.072 m 250 m 250 m 11 32.768 m 62.5 m 62.5 m example :setting watchdog timer interrupt ld sp, 083fh : sets the stack pointer ld (wdtcr1), 00001000b : wdtout 0
page 69 TMP86FS49BFG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 is set to ?1?, a watchdog timer reset request is generated. when a watchdog timer reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] (1.5 s @ fc = 16.0 mhz). note:when a watchdog timer reset is generated in the sl ow1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency cl ock oscillator is restarted. however, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. figure 6-2 watchdog timer interrupt clock binary counter overflow intwdt interrupt request (wdtcr1= "0") 2 17 /fc 2 19 /fc [s] (wdtt=11) write 4e h to wdtcr2 1 2 30 1 2 3 0 internal reset (wdtcr1= "1") a reset occurs
page 70 6. watchdog timer (wdt) 6.3 address trap TMP86FS49BFG 6.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 6.3.1 selection of address tr ap in internal ram (atas) wdtcr1 specifies whether or not to generate address traps in the inte rnal ram area. to execute an instruction in the internal ram area, clear wdtcr1 to ?0?. to enable the wdtcr1 set- ting, set wdtcr1 and then write d2h to wdtcr2. executing an instruction in the sfr or dbr area generates an address trap unconditionally regardless of the setting in wdtcr1. 6.3.2 selection of operati on at address trap (atout) when an address trap is generated, either the inte rrupt request or the reset request can be selected by wdtcr1. 6.3.3 address trap interrupt (intatrap) while wdtcr1 is ?0?, if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is ?1?), dbr or the sfr area, address trap interrupt (intatrap) will be generated. an address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas- ter flag (imf). when an address trap interrupt is generated while the other interrupt including an address trap interrupt is already accepted, the new address trap is processed immediately and the previous interrupt is held pending. therefore, if address trap interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate address trap interrupts, set the stack pointer beforehand. watchdog timer control register 1 wdtcr1 (0034h) 7654 3 21 0 atas atout (wdten) (wdtt) (wdtout) (initial value: **11 1001) atas select address trap generation in the internal ram area 0: generate no address trap 1: generate address traps (after setting atas to ?1?, writing the control code d2h to wdtcr2 is required) write only atout select operation at address trap 0: interrupt request 1: reset request watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code and address trap area control code d2h: enable address trap area selection (atrap control code) 4eh: clear the watchdog timer binary counter (wdt clear code) b1h: disable the watchdog timer (wdt disable code) others: invalid write only
page 71 TMP86FS49BFG 6.3.4 address trap reset while wdtcr1 is ?1?, if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is ?1?), dbr or the sfr area, address trap reset will be generated. when an address trap reset request is generated, the in ternal hardware is reset. the reset time is maximum 24/fc [s] (1.5 s @ fc = 16.0 mhz). note:when an address trap reset is generated in the slow1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency cl ock oscillator is restarted. however, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors.
page 72 6. watchdog timer (wdt) 6.3 address trap TMP86FS49BFG
page 73 TMP86FS49BFG 7. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 7.1 time base timer 7.1.1 configuration figure 7-1 time base timer configuration 7.1.2 control time base timer is controlled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], fs ; low-frequency clock [hz], *; don't care time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 ? 011 fc/2 14 fs/2 6 ? 100 fc/2 13 fs/2 5 ? 101 fc/2 12 fs/2 4 ? 110 fc/2 11 fs/2 3 ? 111 fc/2 9 fs/2 ? fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request
page 74 7. time base timer (tbt) 7.1 time base timer TMP86FS49BFG note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. 7.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generator which is selected by tb tck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirl) . 7 table 7-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 ? 011 976.56 512 ? 100 1953.13 1024 ? 101 3906.25 2048 ? 110 7812.5 4096 ? 111 31250 16384 ? source clock enable tbt interrupt period tbtcr inttbt
page 75 TMP86FS49BFG 7.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 7.2.1 configuration figure 7-3 divider output 7.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 tbtcr output latch port output latch mpx dvoen tbtcr dvo pin output dvock divider output control register (a) configuration (b) timing chart data output 2 a b c y d s d q dvo pin fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 10 or fs/2 2
page 76 7. time base timer (tbt) 7.2 divider output (dvo) TMP86FS49BFG example :1.95 khz pulse output (fc = 16.0 mhz) ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 7-2 divider output frequency ( exam ple : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k
page 77 TMP86FS49BFG 8. 16-bit timercounter 1 (tc1) 8.1 configuration figure 8-1 timercounter 1 (tc1) :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3
page 78 8. 16-bit timercounter 1 (tc1) 8.2 timercounter control TMP86FS49BFG 8.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and time r f/f control, write to tc1cr during tc1s=00. set the timer f/ f1 control until the first timer start after setting the ppg mode. timer register 1514131211109876543210 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write e nabled only in the ppg output mode) timercounter 1 control register tc1cr (0026h) 76543210 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap1 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett1 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg1 ppg output control 0:continuous pulse generation 1:one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 ? 10 fc/2 3 fc/2 3 dv1 ? 11 external clock (tc1 pin input) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w
page 79 TMP86FS49BFG note 4: auto-capture can be used only in t he timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to ?0? in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to ?00? automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after th e execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time.
page 80 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG 8.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interr upt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr to ?1? captures the up-counter value into the timer reg- ister 1b (tc1drb) with the auto-capture function. use the auto-capture function in the operative conditio n of tc1. a cap- tured value may not be fixed if it's read after the execution of the timer stop or auto-capture disa ble. read the capture value in a capture enabled condition. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at leas t one cycle of the internal source clock before reading tc1drb for the first time. note: since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. table 8-1 internal source clock for timercounter 1 (example: fc = 16 mhz, fs = 32.768 khz) tc1ck normal1/2, idle1/2 mode slow, sleep mode dv7ck = 0 dv7ck = 1 resolution [ s] maximum time setting [s] resolution [ s] maximum time setting [s] resolution [ s] maximum time set- ting [s] 00 128 8.39 244.14 16.0 244.14 16.0 01 8.0 0.524 8.0 0.524 ? ? 10 0.5 32.77 m 0.5 32.77 m ? ? example 1 :setting the timer mode with source clock fc/2 11 [hz] and generating an interrupt 1 second later (fc = 16 mhz, tbtcr = ?0?) ldw (tc1dra), 1e84h ; sets the timer register (1 s 2 11 /fc = 1e84h) di ; imf = ?0? set (eirl). 5 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00000000b ; selects the source clock and mode ld (tc1cr), 00010000b ; starts tc1 example 2 :auto-capture ld (tc1cr), 01010000b ; acap1 1 : : ld wa, (tc1drb) ; reads the capture value
page 81 TMP86FS49BFG figure 8-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1
page 82 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG 8.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr. ? when tc1cr is set to ?1? (trigger st art and stop) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. if the edge opposite to trigger edge is detected before detecting a match between the up-counter and the tc1dra, the up-counter is cleared and ha lted without generating an interrupt request. therefore, this mode can be used to det ect exceeding the specified pulse by interrupt. after being halted, the up-count er restarts counting when th e trigger edge is detected. ? when tc1cr is set to ?0? (trigger start) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. the edge opposite to the trigger edge has no effect in count up. the trigger edge for the next count- ing is ignored if detecting it before detectin g a match between the up-counter and the tc1dra. since the tc1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. a pulse width of 12/fc [s] or more is required to ensure edge detectio n. the rejection circuit is turned off in the slow1/2 or sleep1/2 mode, but a pulse width of one machine cycl e or more is required. example 1 :generating an interrupt 1 ms after the rising edge of the input pulse to the tc1 pin (fc =16 mhz) ldw (tc1dra), 007dh ; 1ms 2 7 /fc = 7dh di ; imf = ?0? set (eirl). 5 ; enables inttc1 interrupt ei ; imf = ?1? ld (tc1cr), 00000100b ; selects the source clock and mode ld (tc1cr), 00100100b ; starts tc1 external trigger, mett1 = 0 example 2 :generating an interrupt when the low-level pulse with 4 ms or more width is input to the tc1 pin (fc =16 mhz) ldw (tc1dra), 01f4h ; 4 ms 2 7 /fc = 1f4h di ; imf = ?0? set (eirl). 5 ; enables inttc1 interrupt ei ; imf = ?1? ld (tc1cr), 00000100b ; selects the source clock and mode ld (tc1cr), 01110100b ; starts tc1 external trigger, mett1 = 1
page 83 TMP86FS49BFG figure 8-3 external tri gger timer mode timing chart inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear
page 84 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG 8.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is se lected as the count up edge in tc1cr. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at each edge of the input pulse to the tc1 pin. since a match between the up-counter and the value set to tc1dra is detected at the edge opposite to the selected edge, an inttc1 interrupt request is generated after a match of the value at the edge opposite to the selected edge. two or more machine cycles are required for th e low-or high-level pulse input to the tc1 pin. setting tc1cr to ?1? captures the up-counter value into tc1drb with the auto capture function. use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the captu re value in a captu re enabled condi- tion. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". theref ore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. figure 8-4 event c ounter mode timing chart table 8-2 input pulse width to tc1 pin minimum pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode high-going 2 3 /fc 2 3 /fs low-going 2 3 /fc 2 3 /fs at the rising edge (tc1s = 10) inttc1 interrput request tc1 pin input up-counter tc1dra ? 2 1 0 n timer start 2 1 0 n match detect counter clear n ? 1
page 85 TMP86FS49BFG 8.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. eith er the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc1cr. figure 8-5 window mode timing chart match detect tc1dra inttc1 interrput request interrput request internal clock counter tc1dra tc1 pin input internal clock counter tc1 pin input inttc1 (a) positive logic (tc1s = 10) (b) negative logic (tc1s = 11) ? ? match detect 1 0 7 47 5 46 31 2 1 0 7 5 3 6 2 0 2 3 counter clear timer start 890 1 9 timer start counter clear count start count stop count start count start count stop count start
page 86 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG 8.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr< tc1s>. either the single- or double-e dge capture is selected as the trig- ger edge in tc1cr. ? when tc1cr is set to ?1? (single-edge capture) either high- or low-level input pulse width can be measured. to measure the high-level input pulse width, set the rising edge to tc1cr. to measure the low-level input pulse width, set the falling edge to tc1cr. when detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to tc1drb and generates an inttc1 interrupt request. the up-counter is cleared at this time, a nd then restarts counting wh en detecting the trigger edge used to start counting. ? when tc1cr is set to ?0? (double-edge capture) the cycle starting with either the high- or low-going input pulse can be measured. to measure the cycle starting with the high-going pulse, set the ri sing edge to tc1cr. to measure the cycle starting with the low-going pulse, set the falling edge to tc1cr. when detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to tc1drb and generates an inttc1 interrupt request. the up-counter continues counting up, a nd captures the up-counter value into tc1drb and generates an inttc1 interrupt request when detecting the trigger edge used to start counting. the up-counter is cleared at this time, and then continues counting. note 1: the captured value must be read from tc1drb until the next trigger edge is detected. if not read, the cap- tured value becomes a don?t care. it is recommended to us e a 16-bit access instruction to read the captured value from tc1drb. note 2: for the single-edge capture, the counter after capt uring the value stops at ?1? until detecting the next edge. therefore, the second captured value is ?1? larger than the captured value i mmediately after counting starts. note 3: the first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value.
page 87 TMP86FS49BFG example :duty measurem ent (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 serv ice switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf = ?0? set (eirl). 5 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector width hpulse tc1 pin inttc1 interrupt request inttc1sw
page 88 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG figure 8-6 pulse wi dth measurement mode tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture
page 89 TMP86FS49BFG 8.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1c r specifies either the edge of the input pulse to the tc1 pin or the command start. tc1cr specifies whether a duty pulse is produced continuously or not (one-shot pulse). ? when tc1cr is set to ?0? (continuous pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter contin- ues counting. when a match between the up-counter and the tc1dra value is detected, the level of the ppg pin is inverted and an inttc1 interrupt requ est is generated. the up-counter is cleared at this time, and then continues counting and pulse generation. when tc1s is cleared to ?00? during ppg output, the ppg pin retains the level immediately before the counter stops. ? when tc1cr is set to ?1? (one-shot pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter contin- ues counting. when a match between the up-counter and the tc1dra value is detected, the level of the ppg pin is inverted and an inttc1 interrupt re quest is generated. tc1cr is cleared to ?00? automatically at this time, and the timer stops. the pulse generated by ppg retains the same level as that when the timer stops. since the output level of the ppg pin can be set with tc1cr when the timer starts, a positive or neg- ative pulse can be generated. since the inverted level of the timer f/f1 output level is output to the ppg pin, specify tc1cr to ?0? to set the high level to the ppg pin, and ?1? to set the low level to the ppg pin. upon reset, the timer f/f1 is initialized to ?0?. note 1: to change tc1dra or tc1drb during a run of the ti mer, set a value sufficiently larger than the count value of the counter. setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. note 2: do not change tc1cr during a run of the ti mer. tc1cr can be set correctly only at initial- ization (after reset). when the timer stops during pp g, tc1cr can not be set correctly from this point onward if the ppg output has the level which is inverted of the level when the timer starts. (setting tc1cr specifies the timer f/f1 to the level inverted of the programmed value.) therefore, the timer f/f1 needs to be initialized to ensure an arbitrar y level of the ppg output. to initialize the timer f/f1, change tc1cr to the timer mode (it is not required to start the timer mode), and then set the ppg mode. set tc1cr at this time. note 3: in the ppg mode, the follow ing relationship must be satisfied. tc1dra > tc1drb note 4: set tc1drb after changing the mode of tc1m to the ppg mode.
page 90 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG figure 8-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc ms = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer :: ld (tc1cr), 10000111b ; stops the timer ld (tc1cr), 10000100b ; sets the timer mode ld (tc1cr), 00000111b ; sets the ppg mode, tff1 = 0 ld (tc1cr), 00010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr write to tc1cr internal reset match to tc1drb match to tc1dra tc1cr clear timer f/f1 inttc1 interrupt request
page 91 TMP86FS49BFG figure 8-8 pp g mode timing chart inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output
page 92 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49BFG
page 93 TMP86FS49BFG 9. 16-bit timer/counter2 (tc2) 9.1 configuration note: when control input/output is used, i/o port setting should be set correctly. for det ails, refer to the section "i/o ports" . figure 9-1 time r/counter2 (tc2) c d f tc2 control register tc2 pin tc2cr 16-bit up counter tc2dr clear tc2s tc2ck source clock timer/ event counter window tc2s 16-bit timer register 2 3 h a b e s b a s y inttc2 interrupt port (note) cmp tc2m fc fs match fc/2 23, fs/2 15 fc/2 8 fc/2 3 fc/2 13, fs/2 5
page 94 9. 16-bit timer/counter2 (tc2) 9.2 control TMP86FS49BFG 9.2 control the timer/counter 2 is controlled by a timer/counter 2 control register (tc2cr) and a 16-bit timer register 2 (tc2dr). note 1: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don't care note 2: when writing to the timer register 2 (tc2dr), always write to the lower side (tc2drl) and then the upper side (tc2drh) in that order. writing to only the lower side (tc2drl) or the upper side (tc2drh) has no effect. note 3: the timer register 2 (tc2dr) uses the value previously set in it for coinci dence detection until data is written to the upper side (tc2drh) after writing data to the lower side (tc2drl). note 4: set the mode and source clock when the tc2 stops (tc2s = 0). note 5: values to be loaded to the timer regi ster must satisfy the following condition. tc2dr > 1 (tc2dr 15 to tc2dr 11 > 1 at warm up) note 6: if a read instruction is executed for tc2cr, read data of bit 7, 6 and 1 are unstable. note 7: the high-frequency clock (fc) canbe selected on ly when the time mode at slow2 mode is selected. note 8: on entering stop mode, the tc2 start control (tc2s) is cl eared to "0" automatically. so, the timer stops. once the stop mode has been released, to start using the timer counter, set tc2s again. tc2dr (0025h, 0024h) 1514131211109876543210 tc2drh (0025h) tc2drl (0024h) (initial value: 1111 1111 1111 1111) r/w tc2cr (0023h) 76543210 tc2s tc2ck tc2m (initial value: **00 00*0) tc2s tc2 start control 0:stop and counter clear 1:start r/w tc2ck tc2 source clock select unit : [hz] normal1/2, idle1/2 mode divider slow1/2 mode sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 dv21 fs/2 15 fs/2 15 001 fc/2 13 fs/2 5 dv11 fs/2 5 fs/2 5 010 fc/2 8 fc/2 8 dv6 ? ? 011 fc/2 3 fc/2 3 dv1 ? ? 100 ? ? ? fc (note7) ? 101 fs fs ? ? ? 110 reserved external clock (tc2 pin input) 111 tc2m tc2 operating mode select 0:timer/event counter mode 1:window mode r/w
page 95 TMP86FS49BFG 9.3 function the timer/counter 2 has three operating modes: timer, event counter and window modes. and if fc or fs is selected as th e source clock in timer mode, when sw itching the timer mode from slow1 to normal2, the timer/counter2 can generate warm-up time until the oscillator is stable. 9.3.1 timer mode in this mode, the internal clock is used for counting up. the contents of tc2dr are compared with the con- tents of up counter. if a match is found, a timer/counter 2 interrupt (inttc2) is generated, and the counter is cleared. counting up is resumed after the counter is cleared. when fc is selected for source cl ock at slow2 mode, lower 11-bits of tc2dr are ignored and generated a interrupt by matching upper 5-bits only. though, in this situation, it is necessary to set tc2drh only. note:when fc is selected as the source clock in timer mo de, it is used at warm-up for switching from slow1 mode to normal2 mode. table 9-1 source clock (internal clock) for timer/counter2 (at fc = 16 mhz, dv7ck=0) tc2c k normal1/2, idle1/2 mode slow1/2 mode sleep1/2 mode dv7ck = 0 dv7ck = 1 resolution maximum time set- ting resolution maximum time set- ting resolu- tion maxi- mum time setting resolu- tion maxi- mum time setting 000 524.29 [ms] 9.54 [h] 1 [s] 18.2 [h] 1 [s] 18.2 [h] 1 [s] 18.2 [h] 001 512.0 [ms] 33.55 [s] 0.98 [ms] 1.07 [min] 0.98 [ms] 1.07 [min] 0.98 [ms] 1.07 [min] 010 16.0 [ms] 1.05 [s] 16.0 [ms] 1.05 [s] ? ? ? ? 011 0.5 [ms] 32.77 [ms] 0.5 [ms] 32.77 [ms] ? ? ? ? 100 ? ? ? ? 62.5 [ns] ? ? ? 101 30.52 [ms] 2 [s] 30.52 [ms] 2 [s] ? ? ? ? example :sets the timer m ode with source clock fc/2 3 [hz] and generates an interrupt every 25 ms (at fc = 16 mhz ) ldw (tc2dr), 061ah ; sets tc2dr (25 ms 3 2 8 /fc = 061ah) di ; imf= ?0? set (eire). 6 ; enables inttc2 interrupt ei ; imf= ?1? ld (tc2cr), 00001000b ; source clock / mode select ld (tc2cr), 00101000b ; starts timer
page 96 9. 16-bit timer/counter2 (tc2) 9.3 function TMP86FS49BFG figure 9-2 timer mode timing chart inttc2 interrupt source clock up-counter tc2dr match detect counter clear timer start 01234 n 0 123 :?
page 97 TMP86FS49BFG 9.3.2 event counter mode in this mode, events are counted on the rising edge of the tc2 pin input. the contents of tc2dr are com- pared with the contents of the up counter. if a match is found, an inttc2 interrupt is generated, and the counter is cleared. counting up is resumed every the rising edge of the tc2 pin input after the up counter is cleared. match detect is executed on the falling edge of the tc2 pin. therefore, an inttc2 interrupt is generated at the falling edge after the match of tc2dr and up counter. the minimum input pulse width of tc2 pin is shown in table 9-2. two or more machine cycles are required for both the ?h? and ?l? levels of the pulse width. figure 9-3 event c ounter mode timing chart 9.3.3 window mode in this mode, counting up performed on the rising edge of an internal clock during tc2 external pin input (window pulse) is ?h? level. the contents of tc2dr are co mpared with the contents of up counter. if a match found, an inttc2 interrupt is genera ted, and the up-counter is cleared. the maximum applied frequency (tc2 input) must be considerably slower than the selected internal clock by the tc2cr. note:it is not available window mode in the slow/sl eep mode. therefore, at the window mode in normal mode, the timer should be halted by setting tc2cr to "0" before the slow/sleep mode is entered. example :sets the event counter mode and gene rates an inttc2 interrupt 640 counts later. ldw (tc2dr), 640 ; sets tc2dr di ; imf= ?0? set (eire). 6 ;enables inttc2 interrupt ei ; imf= ?1? ld (tc2cr), 00011100b ; tc2 source vclock / mode select ld (tc2cr), 00111100b ; starts tc2 table 9-2 timer/counter 2 external input clock pulse width minimum input pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode ?h? width 2 3 /fc 2 3 /fs ?l? width 2 3 /fc 2 3 /fs n inttc2 interrupt tc2 pin input counter tc2dr match detect counter clear timer start 0 1 2 3 n 0 1 2 3
page 98 9. 16-bit timer/counter2 (tc2) 9.3 function TMP86FS49BFG figure 9-4 window mode timing chart example :generates an interrupt , inputting ?h? level pulse width of 120 ms or more. (at fc = 16 mhz, tbtcr = ?0? ) ldw (tc2dr), 00eah ; sets tc2dr (120 ms 3 213 /fc = 00eah) di ; imf= ?0? set (eire). 6 ; enables inttc2 interrupt ei ; imf= ?1? ld (tc2cr), 00000101b ; tc2sorce clock / mode select ld (tc2cr), 00100101b ; starts tc2 match detect :? :? inttc2 interrupt internal clock counter tc2dr tc2 pin input counter clear 12 3 n 0 1 2 timer start
page 99 TMP86FS49BFG 10. 8-bit timercounter (tc3, tc4) 10.1 configuration figure 10-1 8-bit ti mercounter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3
page 100 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG 10.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer opera- tion (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc4cr, where tc3m must be fixed to 011. note 5: to use the timercounter in the 16-bit mode, select the source clock by programming tc3ck. set the timer start control and timer f/f control by programming tc4 cr and tc4cr, respectively. note 6: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 10-1 and table 10-2. timercounter 3 timer register ttreg3 (0014h) r/w 76543210 (initial value: 1111 1111) pwreg3 (0018h) r/w 76543210 (initial value: 1111 1111) timercounter 3 control register tc3cr (0027h) 76543210 tff3 tc3ck tc3s tc3m (initial value: 0000 0000) tff3 time f/f3 control 0: 1: clear set r/w tc3ck operating clock selection [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 ? 010 fc/2 5 fc/2 5 ? 011 fc/2 3 fc/2 3 ? 100 fs fs fs 101 fc/2 fc/2 ? 110 fc fc fc (note 8) 111 tc3 pin input tc3s tc3 start control 0: 1: operation stop and counter clear operation start r/w tc3m tc3m operating mode select 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (each mode is selectable with tc4m.) reserved r/w
page 101 TMP86FS49BFG note 7: the timer register settings are limited depending on t he timer operating mode. for the detailed descriptions, see table 10- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode.
page 102 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc3 over flow signal regardless of the tc4ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr must be set to 011. timercounter 4 timer register ttreg4 (0015h) r/w 76543210 (initial value: 1111 1111) pwreg4 (0019h) r/w 76543210 (initial value: 1111 1111) timercounter 4 control register tc4cr (0028h) 76543210 tff4 tc4ck tc4s tc4m (initial value: 0000 0000) tff4 timer f/f4 control 0: 1: clear set r/w tc4ck operating clock selection [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 ? 010 fc/2 5 fc/2 5 ? 011 fc/2 3 fc/2 3 ? 100 fs fs fs 101 fc/2 fc/2 ? 110 fc fc ? 111 tc4 pin input tc4s tc4 start control 0: 1: operation stop and counter clear operation start r/w tc4m tc4m operating mode select 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w
page 103 TMP86FS49BFG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc3cr. set the timer start control and timer f/f control by prog ramming tc4s and tff4, respectively. note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 10-1 and table 10-2. note 8: the timer register settings are limited depending on t he timer operating mode. for the detailed descriptions, see table 10- 3. note 1: for 16-bit operations (16-bit timer/event counter, warm- up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock table 10-1 operating mode and selectable source clock (normal1/2 and idle1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer ??? ????? 8-bit event counter ??????? 8-bit pdo ??? ????? 8-bit pwm ?????? ?? 16-bit timer ??? ????? 16-bit event counter ??????? ? warm-up counter ???? ???? 16-bit pwm ??????? ? 16-bit ppg ??? ??? ? table 10-2 operating mode an d selectable source clock (slow1/2 and sleep1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer ???????? 8-bit event counter ??????? ? 8-bit pdo ???????? 8-bit pwm ??? ???? 16-bit timer ???????? 16-bit event counter ??????? ? warm-up counter ?????? ?? 16-bit pwm ??? ?? ? 16-bit ppg ?????? ? note1: note2: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). : available source clock
page 104 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG note: n = 3 to 4 table 10-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3)
page 105 TMP86FS49BFG 10.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 10.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj and ppgj pins may output pulses. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed while the timer is r unning, an expected operation may not be obtained. note 3: j = 3, 4 table 10-4 source clock for timercounter 3, 4 (internal clock) source clock resolution maximum time setting normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 32.6 ms 62.3 ms fc/2 7 fc/2 7 ?8 s ? 2.0 ms ? fc/2 5 fc/2 5 ?2 s ? 510 s? fc/2 3 fc/2 3 ? 500 ns ? 127.5 s? example :setting the timer mode with source clock fc/2 7 hz and generating an interrupt 80 s later (timercounter4, fc = 16.0 mhz) ld (ttreg4), 0ah : sets the timer register (80 s 2 7 /fc = 0ah). di set (eirh). 1 : enables inttc4 interrupt. ei ld (tc4cr), 00010000b : sets the operating clock to fc/2 7 , and 8-bit timer mode. ld (tc4cr), 00011000b : starts tc4.
page 106 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG figure 10-2 8-bit timer mode timing chart (tc4) 10.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the event counter mode, do not change the ttre gj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed whil e the timer is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 10-3 8-bit event counter mode ti ming chart (tc4) 10.3.3 8-bit programmable divi der output (pdo) mode (tc3, 4) this mode is used to generate a pu lse with a 50% duty cycle from the pdoj pin. in the pdo mode, the up-counter counts up using the internal clock. when a match between the up-counter and the ttregj value is detected , the logic level output from the pdoj pin is switched to the opposite state and the up-counter is cleared. the inttcj interrupt request is generated at the time. the logic state opposite to the timer f/fj logic level is output from the pdoj pin. an arbitrary value can be set to the timer f/fj by tcjcr. upon reset, the timer f/fj value is initialized to 0. to use the programmable divider output, set the output latch of the i/o port to 1. 1 2 3 n-1 n 0 1 n-1 n 2 0 1 2 0 n ? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg4 inttc4 interrupt request 1 0 2 n-1 n 0 1 2 0 n ? counter match detect counter clear n-1 n 2 0 1 match detect counter clear tc4cr ttreg4 inttc4 interrupt request tc4 pin input
page 107 TMP86FS49BFG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr setting upon stopping of the timer. example: fixing the pdoj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pdoj pin to the high level. note 3: j = 3, 4 example :generating 1024 hz pulse using tc4 (fc = 16.0 mhz) setting port ld (ttreg4), 3dh : 1/1024 2 7 /fc 2 = 3dh ld (tc4cr), 00010001b : sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc4cr), 00011001b : starts tc4.
page 108 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG figure 10-4 8-bi t pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr tc4cr ttreg4 timer f/f4 pdo 4 pin inttc4 interrupt request
page 109 TMP86FS49BFG 10.3.4 8-bit pulse width modulat ion (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr, positive and negative pulses can be gen- erated. upon reset, the tim er f/fj is cleared to 0. (the logic level output from the pwmj pin is the opposite to the timer f/fj logic level.) since pwregj in the pwm mode is se rially connected to the shift regist er, the value set to pwregj can be changed while the timer is running. the value set to pwregj during a run of the timer is shifted by the inttcj interrupt request and loaded into pwregj. while the timer is stopped, the value is shifted immedi- ately after the programming of pwre gj. if executing the read instruction to pwregj during pwm output, the value in the shift register is read, but not the valu e set in pwregj. therefore, after writing to pwregj, the reading data of pwregj is previo us value until inttcj is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pw regj immediately after the inttcj interrupt request is generated (normally in the inttcj interrupt service r outine.) if the programming of pwregj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next inttcj interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwmj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr upon stopping of the timer. example: fixing the pwmj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pwmj pin to the high level. note 3: to enter the stop mode during pwm output, stop the timer and then enter the stop mode. if the stop mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out- put from the pwmj pin during the warm-up period time after exiting the stop mode. note 4: j = 3, 4 table 10-5 pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 32.8 ms 62.5 ms fc/2 7 fc/2 7 ?8 s?2.05 ms? fc/2 5 fc/2 5 ?2 s ? 512 s? fc/2 3 fc/2 3 ? 500 ns ? 128 s? fs fs fs 30.5 s30.5 s 7.81 ms 7.81 ms fc/2 fc/2 ? 125 ns ? 32 s? fc fc ? 62.5 ns ? 16 s?
page 110 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG figure 10-5 8-bit pwm mode timing chart (tc4) 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr tc4cr pwreg4 timer f/f4 pwm 4 pin inttc4 interrupt request write to pwreg4 write to pwreg4
page 111 TMP86FS49BFG 10.3.5 16-bit time r mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr to 1, an inttc 4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter continues counting. pr ogram the lower byte and upper byte in this order in the timer register. (programming only the uppe r or lower byte should not be attempted.) note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj , and ppgj pins may output a pulse. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after programming of ttregj. therefore, if ttreg j is changed while the time r is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 10-6 16-bit timer m ode timing chart (tc3 and tc4) table 10-6 source clock for 16-bit timer mode source clock resolution maximum time setting normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 fs/2 3 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500 ns ? 32.8 ms ? example :setting the timer mode with source clock fc/2 7 hz, and generating an interrupt 300 ms later (fc = 16.0 mhz) ldw (ttreg3), 927ch : sets the timer register (300 ms 2 7 /fc = 927ch). di set (eirh). 1 : enables inttc4 interrupt. ei ld (tc3cr), 13h :sets the operating clock to fc/2 7 , and 16-bit timer mode (lower byte). ld (tc4cr), 04h : sets the 16-bit timer mode (upper byte). ld (tc4cr), 0ch : starts the timer. 1 0 2 3 mn-1 mn 0 1 mn-1 mn 2 0 1 2 0 n ? m ? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg3 (lower byte) inttc4 interrupt request ttreg4 (upper byte)
page 112 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG 10.3.6 16-bit event c ounter mode (tc3 and 4) 10.3.7 16-bit pulse wi dth modulation (pwm) ou tput mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the pwm 4 pin is the opposite to the timer f/f4 logic level.) since pwreg4 and 3 in the pwm mode are serially connected to the shift register, the values set to pwreg4 and 3 can be changed while the timer is runni ng. the values set to pwreg4 and 3 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg4 and 3. while the timer is stopped, the values are shifted i mmediately after the programming of pwreg4 and 3. set the lower byte (pwreg3) and upper byte (pwreg4) in this order to program pwreg4 and 3. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg4 and 3 during pwm output, the values set in the shift register is read, but not the values set in pwreg4 and 3. therefore, after writing to the pwreg4 and 3, reading data of pwreg4 and 3 is previous value until inttc4 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg4 and 3 immediately after the inttc4 interrupt request is generated (normally in the inttc4 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc4 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not program tc4cr upon stopping of the timer. example: fixing the pwm 4 pin to the high level when the timercounter is stopped in the event counter mode, the up-counter counts up at the falling edge to the tc3 pin. the timercounter 3 and 4 are cascadable to fo rm a 16-bit event counter. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter rest arts counting at the falling edge of the input pulse to the tc3 pin. two machine cycles are required for the low- or high-level pulse input to the tc3 pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/ 2 4 in the slow1/2 or sleep1/2 mode. program the lo wer byte (ttreg3), and upper byte (ttreg4) in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: note 2: note 3: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj and ppgj pins may output pulses. in the event counter mode, do not change the ttregj setti ng while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. j = 3, 4
page 113 TMP86FS49BFG clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 10-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500 ns ? 32.8 ms ? fs fs fs 30.5 s30.5 s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer.
page 114 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG figure 10-7 16-bit pwm mode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr tc4cr pwreg3 (lower byte) timer f/f4 pwm 4 pin inttc4 interrupt request pwreg4 (upper byte) write to pwreg4 write to pwreg4 write to pwreg3 write to pwreg3
page 115 TMP86FS49BFG 10.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the ppg 4 pin is the opposite to the timer f/f4.) set the lower byte and upper byte in this order to program the timer register. (ttreg3 ttreg4, pwreg3 pwreg4) (programming only the upper or lower byte should not be attempted.) for ppg output, set the output latch of the i/o port to 1. note 1: in the ppg mode, do not change the pwregi and ttregi settings while the timer is running. since pwregi and ttregi are not in the shift register c onfiguration in the ppg mode, the new values pro- grammed in pwregi and ttregi are in effect immediately after progra mming pwregi and ttregi. therefore, if pwregi and ttregi are changed whil e the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during ppg output, the ppg 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not change tc4cr upon stopping of the timer. example: fixing the ppg 4 pin to the high level when the timercounter is stopped clr (tc4cr).3: stops the timer clr (tc4cr).7: sets the ppg 4 pin to the high level note 3: i = 3, 4 two machine cycles are required for the high- or low- level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/ 2 or sleep1/2 mode. example :generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ldw (ttreg3), 8002h : sets the cycle period. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and16-bit ppg mode (lower byte). ld (tc4cr), 057h : sets tff4 to the initial value 0, and 16-bit ppg mode (upper byte). ld (tc4cr), 05fh : starts the timer.
page 116 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG figure 10-8 16-bit ppg mode timing chart (tc3 and tc4) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr tc4cr pwreg3 (lower byte) timer f/f4 ppg 4 pin inttc4 interrupt request pwreg4 (upper byte) ttreg3 (lower byte) ttreg4 (upper byte)
page 117 TMP86FS49BFG 10.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercounter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr to 0. if not fixed, the pdoi , pwmi and ppgi pins may output pulses. note 2: in the warm-up counter mode, only upper 8 bits of the timer register ttreg4 and 3 are used for match detection and lower 8 bits are not used. note 3: i = 3, 4 10.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) in this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. before starting the timer, set syscr2 to 1 to oscillate the low-frequency clock. when a match between the up-counter and the timer regist er (ttreg4, 3) value is detected after the timer is started by setting tc4cr to 1, the counter is cleared by generating the inttc4 interrupt request. after stopping the timer in the inttc4 inte rrupt service routine, set syscr2 to 1 to switch the system clock from the high-frequency to low-frequency, and then clear of syscr2 to 0 to stop the high-frequency clock. table 10-8 setting time of low-frequency warm-up counter mode (fs = 32.768 khz) minimum time setting (ttreg4, 3 = 0100h) maximum time setting (ttreg4, 3 = ff00h) 7.81 ms 1.99 s example :after check ing low-frequency clock oscillation stability with tc4 and 3, switching to the slow1 mode set (syscr2).6 : syscr2 1 ld (tc3cr), 43h : sets tff3=0, source clock fs, and 16-bit mode. ld (tc4cr), 05h : sets tff4=0, and warm-up counter mode. ld (ttreg3), 8000h : sets the warm-up time. (the warm-up time depends on the oscillator characteristic.) di : imf 0 set (eirh). 1 : enables the inttc4. ei : imf 1 set (tc4cr).3 : starts tc4 and 3. : : pinttc4: clr (tc4cr).3 : stops tc4 and 3. set (syscr2).5 : syscr2 1 (switches the system clock to the low-frequency clock.) clr (syscr2).7 : syscr2 0 (stops the high-frequency clock.) reti : : vinttc4: dw pinttc4 : inttc4 vector table
page 118 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49BFG 10.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 to 1 to oscillat e the high-frequency clock. when a match between the up-counter and the timer regist er (ttreg4, 3) value is detected after the timer is started by setting tc4cr to 1, the counter is cleared by generating the inttc4 interrupt request. after stopping the timer in the inttc4 inte rrupt service routine, clear syscr2 to 0 to switch the system clock from the low-frequency to high-frequency, and then syscr2 to 0 to stop the low-frequency clock. table 10-9 setting time in high-frequency warm-up counter mode minimum time setting (ttreg4, 3 = 0100h) maximum time setting (ttreg4, 3 = ff00h) 16 s 4.08 ms example :after check ing high-frequency clock oscillation stability with tc4 and 3, switching to the normal1 mode set (syscr2).7 : syscr2 1 ld (tc3cr), 63h : sets tff3=0, source clock fc, and 16-bit mode. ld (tc4cr), 05h : sets tff4=0, and warm-up counter mode. ld (ttreg3), 0f800h : sets the warm-up time. (the warm-up time depends on the oscillator characteristic.) di : imf 0 set (eirh). 1 : enables the inttc4. ei : imf 1 set (tc4cr).3 : starts the tc4 and 3. : : pinttc4: clr (tc4cr).3 : stops the tc4 and 3. clr (syscr2).5 : syscr2 0 (switches the system clock to the high-frequency clock.) clr (syscr2).6 : syscr2 0 (stops the low-frequency clock.) reti : : vinttc4: dw pinttc4 : inttc4 vector table
page 119 TMP86FS49BFG 11. 8-bit timercounter (tc5, tc6) 11.1 configuration figure 11-1 8-bit timercounter 5, 6 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc6cr tc5cr ttreg6 pwreg6 ttreg5 pwreg5 tc5 pin tc6 pin tc6s tc5s inttc5 interrupt request inttc6 interrupt request tff6 tff5 pdo 6/pwm 6/ ppg 6 pin pdo 5/pwm 5/ pin tc5ck tc6ck tc5m tc5s tff5 tc6m tc6s tff6 timer f/f6 timer f/f5
page 120 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG 11.2 timercounter control the timercounter 5 is controlled by the timercounter 5 control register (tc5cr) and two 8-bit timer registers (ttreg5, pwreg5). note 1: do not change the timer register (t treg5) setting while the timer is running. note 2: do not change the timer register (pwreg5) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc5m, tc5ck and tff5 settings while the timer is running. note 3: to stop the timer operation (tc5s= 1 0), do not change the tc5m, tc5ck and tff5 settings. to start the timer opera- tion (tc5s= 0 1), tc5m, tc5ck and tff5 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc6cr, where tc5m must be fixed to 011. note 5: to use the timercounter in the 16-bit mode, select the source clock by programming tc5ck. set the timer start control and timer f/f control by programming tc6 cr and tc6cr, respectively. note 6: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11-1 and table 11-2. timercounter 5 timer register ttreg5 (0016h) r/w 76543210 (initial value: 1111 1111) pwreg5 (001ah) r/w 76543210 (initial value: 1111 1111) timercounter 5 control register tc5cr (0029h) 76543210 tff5 tc5ck tc5s tc5m (initial value: 0000 0000) tff5 time f/f5 control 0: 1: clear set r/w tc5ck operating clock selection [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 ? 010 fc/2 5 fc/2 5 ? 011 fc/2 3 fc/2 3 ? 100 fs fs fs 101 fc/2 fc/2 ? 110 fc fc fc (note 8) 111 tc5 pin input tc5s tc5 start control 0: 1: operation stop and counter clear operation start r/w tc5m tc5m operating mode select 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (each mode is selectable with tc6m.) reserved r/w
page 121 TMP86FS49BFG note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode.
page 122 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG the timercounter 6 is controlled by the timercounter 6 control register (tc6cr) and two 8-bit timer registers (ttreg6 and pwreg6). note 1: do not change the timer register (t treg6) setting while the timer is running. note 2: do not change the timer register (pwreg6) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc6m, tc6ck and tff6 settings while the timer is running. note 3: to stop the timer operation (tc6s= 1 0), do not change the tc6m, tc6ck and tff6 settings. to start the timer operation (tc6s= 0 1), tc6m, tc6ck and tff6 can be programmed. note 4: when tc6m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc5 over flow signal regardless of the tc6ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc6m, where tc5cr must be set to 011. timercounter 6 timer register ttreg6 (0017h) r/w 76543210 (initial value: 1111 1111) pwreg6 (001bh) r/w 76543210 (initial value: 1111 1111) timercounter 6 control register tc6cr (002ah) 76543210 tff6 tc6ck tc6s tc6m (initial value: 0000 0000) tff6 timer f/f6 control 0: 1: clear set r/w tc6ck operating clock selection [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 ? 010 fc/2 5 fc/2 5 ? 011 fc/2 3 fc/2 3 ? 100 fs fs fs 101 fc/2 fc/2 ? 110 fc fc ? 111 tc6 pin input tc6s tc6 start control 0: 1: operation stop and counter clear operation start r/w tc6m tc6m operating mode select 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w
page 123 TMP86FS49BFG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc5cr. set the timer start control and timer f/f control by prog ramming tc6s and tff6, respectively. note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11-1 and table 11-2. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11- 3. note 1: for 16-bit operations (16-bit timer/event counter, warm- up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc5ck). note 2: : available source clock table 11-1 operating mode and selectable source clock (normal1/2 and idle1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc5 pin input tc6 pin input 8-bit timer ??? ????? 8-bit event counter ??????? 8-bit pdo ??? ????? 8-bit pwm ?????? ?? 16-bit timer ??? ????? 16-bit event counter ??????? ? warm-up counter ???? ???? 16-bit pwm ??????? ? 16-bit ppg ??? ??? ? table 11-2 operating mode and selectable source clock (slow1/2 and sleep1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc5 pin input tc6 pin input 8-bit timer ???????? 8-bit event counter ??????? ? 8-bit pdo ???????? 8-bit pwm ??? ???? 16-bit timer ???????? 16-bit event counter ??????? ? warm-up counter ?????? ?? 16-bit pwm ??? ?? ? 16-bit ppg ?????? ? note1: note2: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc5ck). : available source clock
page 124 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG note: n = 5 to 6 table 11-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg6, 5) 65535 warm-up counter 256 (ttreg6, 5) 65535 16-bit pwm 2 (pwreg6, 5) 65534 16-bit ppg 1 (pwreg6, 5) < (ttreg6, 5) 65535 and (pwreg6, 5) + 1 < (ttreg6, 5)
page 125 TMP86FS49BFG 11.3 function the timercounter 5 and 6 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 5 and 6 (tc5, 6) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 11.3.1 8-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj and ppgj pins may output pulses. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed while the timer is r unning, an expected operation may not be obtained. note 3: j = 5, 6 table 11-4 source clock for timercounter 5, 6 (internal clock) source clock resolution maximum time setting normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 32.6 ms 62.3 ms fc/2 7 fc/2 7 ?8 s ? 2.0 ms ? fc/2 5 fc/2 5 ?2 s ? 510 s? fc/2 3 fc/2 3 ? 500 ns ? 127.5 s? example :setting the timer mode with source clock fc/2 7 hz and generating an interrupt 80 s later (timercounter6, fc = 16.0 mhz) ld (ttreg6), 0ah : sets the timer register (80 s 2 7 /fc = 0ah). di set (eire). 2 : enables inttc6 interrupt. ei ld (tc6cr), 00010000b : sets the operating clock to fc/2 7 , and 8-bit timer mode. ld (tc6cr), 00011000b : starts tc6.
page 126 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG figure 11-2 8-bit time r mode timing chart (tc6) 11.3.2 8-bit event counter mode (tc5, 6) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the event counter mode, do not change the ttre gj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed whil e the timer is running, an expected operation may not be obtained. note 3: j = 5, 6 figure 11-3 8-bit event co unter mode timing chart (tc6) 11.3.3 8-bit programmable divi der output (pdo) mode (tc5, 6) this mode is used to generate a pu lse with a 50% duty cycle from the pdoj pin. in the pdo mode, the up-counter counts up using the internal clock. when a match between the up-counter and the ttregj value is detected , the logic level output from the pdoj pin is switched to the opposite state and the up-counter is cleared. the inttcj interrupt request is generated at the time. the logic state opposite to the timer f/fj logic level is output from the pdoj pin. an arbitrary value can be set to the timer f/fj by tcjcr. upon reset, the timer f/fj value is initialized to 0. to use the programmable divider output, set the output latch of the i/o port to 1. 1 2 3 n-1 n 0 1 n-1 n 2 0 1 2 0 n ? internal source clock counter match detect counter clear match detect counter clear tc6cr ttreg6 inttc6 interrupt request 1 0 2 n-1 n 0 1 2 0 n ? counter match detect counter clear n-1 n 2 0 1 match detect counter clear tc6cr ttreg6 inttc6 interrupt request tc6 pin input
page 127 TMP86FS49BFG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr setting upon stopping of the timer. example: fixing the pdoj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pdoj pin to the high level. note 3: j = 5, 6 example :generating 1024 hz pulse using tc6 (fc = 16.0 mhz) setting port ld (ttreg6), 3dh : 1/1024 2 7 /fc 2 = 3dh ld (tc6cr), 00010001b : sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc6cr), 00011001b : starts tc6.
page 128 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG figure 11-4 8-bit pdo mode timing chart (tc6) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc6cr tc6cr ttreg6 timer f/f6 pdo 6 pin inttc6 interrupt request
page 129 TMP86FS49BFG 11.3.4 8-bit pulse width modulat ion (pwm) output mode (tc5, 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr, positive and negative pulses can be gen- erated. upon reset, the tim er f/fj is cleared to 0. (the logic level output from the pwmj pin is the opposite to the timer f/fj logic level.) since pwregj in the pwm mode is se rially connected to the shift regist er, the value set to pwregj can be changed while the timer is running. the value set to pwregj during a run of the timer is shifted by the inttcj interrupt request and loaded into pwregj. while the timer is stopped, the value is shifted immedi- ately after the programming of pwre gj. if executing the read instruction to pwregj during pwm output, the value in the shift register is read, but not the valu e set in pwregj. therefore, after writing to pwregj, the reading data of pwregj is previo us value until inttcj is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pw regj immediately after the inttcj interrupt request is generated (normally in the inttcj interrupt service r outine.) if the programming of pwregj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next inttcj interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwmj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr upon stopping of the timer. example: fixing the pwmj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pwmj pin to the high level. note 3: to enter the stop mode during pwm output, stop the timer and then enter the stop mode. if the stop mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out- put from the pwmj pin during the warm-up period time after exiting the stop mode. note 4: j = 5, 6 table 11-5 pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 32.8 ms 62.5 ms fc/2 7 fc/2 7 ?8 s?2.05 ms? fc/2 5 fc/2 5 ?2 s ? 512 s? fc/2 3 fc/2 3 ? 500 ns ? 128 s? fs fs fs 30.5 s30.5 s 7.81 ms 7.81 ms fc/2 fc/2 ? 125 ns ? 32 s? fc fc ? 62.5 ns ? 16 s?
page 130 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG figure 11-5 8-bit pwm mode timing chart (tc6) 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc6cr tc6cr pwreg6 timer f/f6 pwm 6 pin inttc6 interrupt request write to pwreg6 write to pwreg6
page 131 TMP86FS49BFG 11.3.5 16-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. the timercounter 5 and 6 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg5, ttreg6) valu e is detected after the timer is started by setting tc6cr to 1, an inttc 6 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter continues counting. pr ogram the lower byte and upper byte in this order in the timer register. (programming only the uppe r or lower byte should not be attempted.) note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj , and ppgj pins may output a pulse. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after programming of ttregj. therefore, if ttreg j is changed while the time r is running, an expected operation may not be obtained. note 3: j = 5, 6 figure 11-6 16-bit timer mode timing chart (tc5 and tc6) table 11-6 source clock for 16-bit timer mode source clock resolution maximum time setting normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 fs/2 3 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500 ns ? 32.8 ms ? example :setting the timer mode with source clock fc/2 7 hz, and generating an interrupt 300 ms later (fc = 16.0 mhz) ldw (ttreg5), 927ch : sets the timer register (300 ms 2 7 /fc = 927ch). di set (eire). 2 : enables inttc6 interrupt. ei ld (tc5cr), 13h :sets the operating clock to fc/2 7 , and 16-bit timer mode (lower byte). ld (tc6cr), 04h : sets the 16-bit timer mode (upper byte). ld (tc6cr), 0ch : starts the timer. 1 0 2 3 mn-1 mn 0 1 mn-1 mn 2 0 1 2 0 n ? m ? internal source clock counter match detect counter clear match detect counter clear tc6cr ttreg5 (lower byte) inttc6 interrupt request ttreg6 (upper byte)
page 132 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG 11.3.6 16-bit event c ounter mode (tc5 and 6) 11.3.7 16-bit pulse width modulatio n (pwm) output mode (tc5 and 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 5 and 6 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc6 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc5 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f6 by tc6cr, positive and negative pulses can be generated. upon reset, the timer f/f6 is cleared to 0. (the logic level output from the pwm 6 pin is the opposite to the timer f/f6 logic level.) since pwreg6 and 5 in the pwm mode are serially connected to the shift register, the values set to pwreg6 and 5 can be changed while the timer is runni ng. the values set to pwreg6 and 5 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg6 and 5. while the timer is stopped, the values are shifted i mmediately after the programming of pwreg6 and 5. set the lower byte (pwreg5) and upper byte (pwreg6) in this order to program pwreg6 and 5. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg6 and 5 during pwm output, the values set in the shift register is read, but not the values set in pwreg6 and 5. therefore, after writing to the pwreg6 and 5, reading data of pwreg6 and 5 is previous value until inttc6 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg6 and 5 immediately after the inttc6 interrupt request is generated (normally in the inttc6 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc6 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 6 pin holds the output status when the timer is stopped. to change the output status, program tc6cr after the timer is stopped. do not program tc6cr upon stopping of the timer. example: fixing the pwm 6 pin to the high level when the timercounter is stopped in the event counter mode, the up-counter counts up at the falling edge to the tc5 pin. the timercounter 5 and 6 are cascadable to fo rm a 16-bit event counter. when a match between the up-counter and the timer register (ttreg5, ttreg6) value is detected after the timer is started by setting tc6cr to 1, an inttc6 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter rest arts counting at the falling edge of the input pulse to the tc5 pin. two machine cycles are required for the low- or high-level pulse input to the tc5 pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/ 2 4 in the slow1/2 or sleep1/2 mode. program the lo wer byte (ttreg5), and upper byte (ttreg6) in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: note 2: note 3: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj and ppgj pins may output pulses. in the event counter mode, do not change the ttregj setti ng while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. j = 5, 6
page 133 TMP86FS49BFG clr (tc6cr).3: stops the timer. clr (tc6cr).7 : sets the pwm 6 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 6 pin during the warm-up period time after exiting the stop mode. table 11-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500 ns ? 32.8 ms ? fs fs fs 30.5 s30.5 s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg5), 07d0h : sets the pulse width. ld (tc5cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc6cr), 056h : sets tff6 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc6cr), 05eh : starts the timer.
page 134 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG figure 11-7 16-bit pwm mode timing chart (tc5 and tc6) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc6cr tc6cr pwreg5 (lower byte) timer f/f6 pwm 6 pin inttc6 interrupt request pwreg6 (upper byte) write to pwreg6 write to pwreg6 write to pwreg5 write to pwreg5
page 135 TMP86FS49BFG 11.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc5 and 6) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 5 and 6 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6 ) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg5, ttreg6) value is detected, and the counter is cleared. the inttc6 interrupt is generated at this time. since the initial value can be set to the timer f/f6 by tc6cr, positive and negative pulses can be generated. upon reset, the timer f/f6 is cleared to 0. (the logic level output from the ppg 6 pin is the opposite to the timer f/f6.) set the lower byte and upper byte in this order to program the timer register. (ttreg5 ttreg6, pwreg5 pwreg6) (programming only the upper or lower byte should not be attempted.) for ppg output, set the output latch of the i/o port to 1. note 1: in the ppg mode, do not change the pwregi and ttregi settings while the timer is running. since pwregi and ttregi are not in the shift register c onfiguration in the ppg mode, the new values pro- grammed in pwregi and ttregi are in effect immediately after progra mming pwregi and ttregi. therefore, if pwregi and ttregi are changed whil e the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during ppg output, the ppg 6 pin holds the output status when the timer is stopped. to change the output status, program tc6cr after the timer is stopped. do not change tc6cr upon stopping of the timer. example: fixing the ppg 6 pin to the high level when the timercounter is stopped clr (tc6cr).3: stops the timer clr (tc6cr).7: sets the ppg 6 pin to the high level note 3: i = 5, 6 two machine cycles are required for the high- or low- level pulse input to the tc5 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/ 2 or sleep1/2 mode. example :generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 mhz) setting ports ldw (pwreg5), 07d0h : sets the pulse width. ldw (ttreg5), 8002h : sets the cycle period. ld (tc5cr), 33h : sets the operating clock to fc/2 3 , and16-bit ppg mode (lower byte). ld (tc6cr), 057h : sets tff6 to the initial value 0, and 16-bit ppg mode (upper byte). ld (tc6cr), 05fh : starts the timer.
page 136 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG figure 11-8 16-bit ppg m ode timing chart (tc5 and tc6) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc6cr tc6cr pwreg5 (lower byte) timer f/f6 ppg 6 pin inttc6 interrupt request pwreg6 (upper byte) ttreg5 (lower byte) ttreg6 (upper byte)
page 137 TMP86FS49BFG 11.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 5 and 6 are cascadable to form a 16-bit timercounter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr to 0. if not fixed, the pdoi , pwmi and ppgi pins may output pulses. note 2: in the warm-up counter mode, only upper 8 bits of the timer register ttreg6 and 5 are used for match detection and lower 8 bits are not used. note 3: i = 5, 6 11.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) in this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. before starting the timer, set syscr2 to 1 to oscillate the low-frequency clock. when a match between the up-counter and the timer regist er (ttreg6, 5) value is detected after the timer is started by setting tc6cr to 1, the counter is cleared by generating the inttc6 interrupt request. after stopping the timer in the inttc6 inte rrupt service routine, set syscr2 to 1 to switch the system clock from the high-frequency to low-frequency, and then clear of syscr2 to 0 to stop the high-frequency clock. table 11-8 setting time of low-frequency warm-up counter mode (fs = 32.768 khz) minimum time setting (ttreg6, 5 = 0100h) maximum time setting (ttreg6, 5 = ff00h) 7.81 ms 1.99 s example :after check ing low-frequency clock oscillation stability with tc6 and 5, switching to the slow1 mode set (syscr2).6 : syscr2 1 ld (tc5cr), 43h : sets tff5=0, source clock fs, and 16-bit mode. ld (tc6cr), 05h : sets tff6=0, and warm-up counter mode. ld (ttreg5), 8000h : sets the warm-up time. (the warm-up time depends on the oscillator characteristic.) di : imf 0 set (eire). 2 : enables the inttc6. ei : imf 1 set (tc6cr).3 : starts tc6 and 5. : : pinttc6: clr (tc6cr).3 : stops tc6 and 5. set (syscr2).5 : syscr2 1 (switches the system clock to the low-frequency clock.) clr (syscr2).7 : syscr2 0 (stops the high-frequency clock.) reti : : vinttc6: dw pinttc6 : inttc6 vector table
page 138 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49BFG 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 to 1 to oscillat e the high-frequency clock. when a match between the up-counter and the timer regist er (ttreg6, 5) value is detected after the timer is started by setting tc6cr to 1, the counter is cleared by generating the inttc6 interrupt request. after stopping the timer in the inttc6 inte rrupt service routine, clear syscr2 to 0 to switch the system clock from the low-frequency to high-frequency, and then syscr2 to 0 to stop the low-frequency clock. table 11-9 setting time in high-frequency warm-up counter mode minimum time setting (ttreg6, 5 = 0100h) maximum time setting (ttreg6, 5 = ff00h) 16 s 4.08 ms example :after check ing high-frequency clock oscillation stability with tc6 and 5, switching to the normal1 mode set (syscr2).7 : syscr2 1 ld (tc5cr), 63h : sets tff5=0, source clock fc, and 16-bit mode. ld (tc6cr), 05h : sets tff6=0, and warm-up counter mode. ld (ttreg5), 0f800h : sets the warm-up time. (the warm-up time depends on the oscillator characteristic.) di : imf 0 set (eire). 2 : enables the inttc6. ei : imf 1 set (tc6cr).3 : starts the tc6 and 5. : : pinttc6: clr (tc6cr).3 : stops the tc6 and 5. clr (syscr2).5 : syscr2 0 (switches the system clock to the high-frequency clock.) clr (syscr2).6 : syscr2 0 (stops the low-frequency clock.) reti : : vinttc6: dw pinttc6 : inttc6 vector table
page 139 TMP86FS49BFG 12. asynchronous serial interface (uart1 ) 12.1 configuration figure 12-1 uart1 (asynch ronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexer uart1cr1 td1buf rd1buf inttxd1 intrxd1 uart1sr uart1cr2 rxd1 txd1 inttc3
page 140 12. asynchronous serial interface (uart1 ) 12.2 control TMP86FS49BFG 12.2 control uart1 is controlled by the uart1 control registers (uart1cr1, uart1cr2). the operating status can be monitored using the uart status register (uart1sr). note 1: when operations are disabled by se tting txe and rxe bit to ?0?, the setting be comes valid when data transmit or receive complete. when the transmit data is stored in the transmit data buf fer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uart1cr1 and uart1cr1 should be set to ?0? before uart1cr1 is changed. note: when uart1cr2 = ?01?, pulses longer than 96/fc [s] are always regarded as signals; when uart1cr2 = ?10?, longer than 192/fc [s]; and when uart1cr2 = ?11?, longer than 384/fc [s]. uart1 control register1 uart1cr1 (0f95h) 76543210 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 tc3 ( input inttc3) fc/96 uart1 control register2 uart1cr2 (0f96h) 7654321 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejection time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits
page 141 TMP86FS49BFG note: when an inttxd is generated, tbep flag is set to "1" automatically. uart1 status register uart1sr (0f95h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart1 receive data buffer rd1buf (0f97h) 76543210read only (initial value: 0000 0000) uart1 transmit data buffer td1buf (0f97h) 76543210write only (initial value: 0000 0000)
page 142 12. asynchronous serial interface (uart1 ) 12.3 transfer data format TMP86FS49BFG 12.3 transfer data format in uart1, an one-bit start bit (low level), stop bit (b it length selectable at high level, by uart1cr1), and parity (select parity in uart1cr1; even- or odd-numbered parity by uart1cr1) are added to the transfer data. the transfer da ta formats are shown as follows. figure 12-2 tran sfer data format figure 12-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 12-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 143 TMP86FS49BFG 12.4 transfer rate the baud rate of uart1 is set of uart1cr1. th e example of the baud rate are shown as follows. when tc3 is used as the uart1 transfer rate (when uart1cr1 = ?110?), the transfer clock and transfer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 12.5 data sampling method the uart1 receiver keeps sampling input using the clock selected by uart1cr1 until a start bit is detected in rxd1 pin input. rt clock starts detecting ?l? level of the rxd1 pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sample d at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to major- ity rule (the data are the same tw ice or more out of three samplings). figure 12-4 data sampling method table 12-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd1 pin rxd1 pin
page 144 12. asynchronous serial interface (uart1 ) 12.6 stop bit length TMP86FS49BFG 12.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uart1cr1. 12.7 parity set parity / no parity by uart1cr1 and set parity type (odd- or even-numbered) by uart1cr1. 12.8 transmit/receive operation 12.8.1 data transmit operation set uart1cr1 to ?1?. read uart1sr to check uart1sr = ?1?, then write data in td1buf (transmit data buffer). writing data in td1buf zero-clears uart1sr< tbep>, transfers the data to the transmit shift register and the data are sequentiall y output from the txd1 pin. the data output include a one-bit start bit, stop bits whose number is specified in uart1cr1 and a par ity bit if parity addition is specified. select the data transfer baud rate usin g uart1cr1. when data transmit starts, transmit buffer empty flag uart1sr is set to ?1? and an inttxd1 interrupt is generated. while uart1cr1 = ?0? and from when ?1? is wr itten to uart1cr1 to when send data are written to td1buf, the txd1 pin is fixed at high level. when transmitting data, first read uart1sr, then write data in td 1buf. otherwise, uart1sr is not zero-cleared and transmit does not start. 12.8.2 data receive operation set uart1cr1 to ?1?. when data are received vi a the rxd1 pin, the receive data are transferred to rd1buf (receive data buffer). at this time, the data transmitted includes a st art bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rd1buf (receive data buffer). then the receive buffe r full flag uart1sr is set and an intrxd1 interrupt is generated. select the data transfer baud rate using uart1cr1. if an overrun error (o err) occurs when data are received, the da ta are not transferre d to rd1buf (receive data buffer) but discarded; data in the rd1buf are not affected. note:when a receive operation is dis abled by setting uart1cr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 145 TMP86FS49BFG 12.9 status flag 12.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uart1sr is set to ?1?. the uart1sr is cleared to ?0? when the rd1buf is read after reading the uart1sr. figure 12-5 generati on of parity error 12.9.2 framing error when ?0? is sampled as the stop bit in the receive da ta, framing error flag uart1sr is set to ?1?. the uart1sr is cleared to ?0? when th e rd1buf is read after reading the uart1sr. figure 12-6 generati on of framing error 12.9.3 overrun error when all bits in the next data are received while unread data are still in rd1buf, overrun error flag uart1sr is set to ?1?. in this case, the receive data is discarded; data in rd1buf are not affected. the uart1sr is cleared to ?0? when th e rd1buf is read after reading the uart1sr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd1 pin uart1sr intrxd1 interrupt after reading uart1sr then rd1buf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd1 pin uart1sr intrxd1 interrupt after reading uart1sr then rd1buf clears ferr.
page 146 12. asynchronous serial interface (uart1 ) 12.9 status flag TMP86FS49BFG figure 12-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uart1sr is cleared. 12.9.4 receive data buffer full loading the received data in rd1buf sets receive data buffer full flag uart1sr to "1". the uart1sr is cleared to ?0? when the rd1buf is read afte r reading the uart1sr. figure 12-8 generat ion of receive data buffer full note:if the overrun error flag uart1sr is set during the period between reading the uart1sr and read- ing the rd1buf, it cannot be cleared by only reading t he rd1buf. therefore, after reading the rd1buf, read the uart1sr again to check whether or not the overrun error flag which should have been cleared still remains set. 12.9.5 transmit data buffer empty when no data is in the transmit buffer td1buf, that is, when data in td1buf are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag uart1sr is set to ?1?. the uart1sr is cleared to ?0? when the td 1buf is written after reading the uart1sr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd1 pin uart1sr intrxd1 interrupt after reading uart1sr then rd1buf clears oerr. rd1buf uart1sr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd1 pin uart1sr intrxd1 interrupt rd1buf after reading uart1sr then rd1buf clears rbfl.
page 147 TMP86FS49BFG figure 12-9 generation of transmit data buffer empty 12.9.6 transmit end flag when data are transmitted and no data is in td1buf (uart1sr = ?1?), transmit end flag uart1sr is set to ?1?. the uart1sr is cleared to ?0? when the data transmit is started after writing the td1buf. figure 12-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 td1buf txd1 pin uart1sr inttxd1 interrupt after reading uart1sr writing td1buf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd1 pin uart1sr uart1sr inttxd1 interrupt data write for td1buf
page 148 12. asynchronous serial interface (uart1 ) 12.9 status flag TMP86FS49BFG
page 149 TMP86FS49BFG 13. asynchronous serial interface (uart2 ) 13.1 configuration figure 13-1 uart2 (asynch ronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexer uart2cr1 td2buf rd2buf inttxd2 intrxd2 uart2sr uart2cr2 rxd2 txd2 inttc5
page 150 13. asynchronous serial interface (uart2 ) 13.2 control TMP86FS49BFG 13.2 control uart2 is controlled by the uart2 control registers (uart2cr1, uart2cr2). the operating status can be monitored using the uart status register (uart2sr). note 1: when operations are disabled by se tting txe and rxe bit to ?0?, the setting be comes valid when data transmit or receive complete. when the transmit data is stored in the transmit data buf fer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uart2cr1 and uart2cr1 should be set to ?0? before uart2cr1 is changed. note: when uart2cr2 = ?01?, pulses longer than 96/fc [s] are always regarded as signals; when uart2cr2 = ?10?, longer than 192/fc [s]; and when uart2cr2 = ?11?, longer than 384/fc [s]. uart2 control register1 uart2cr1 (0f98h) 76543210 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 tc5 ( input inttc5) fc/96 uart2 control register2 uart2cr2 (0f99h) 7654321 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejection time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits
page 151 TMP86FS49BFG note: when an inttxd is generated, tbep flag is set to "1" automatically. uart2 status register uart2sr (0f98h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart2 receive data buffer rd2buf (0f9ah) 76543210read only (initial value: 0000 0000) uart2 transmit data buffer td2buf (0f9ah) 76543210write only (initial value: 0000 0000)
page 152 13. asynchronous serial interface (uart2 ) 13.3 transfer data format TMP86FS49BFG 13.3 transfer data format in uart2, an one-bit start bit (low level), stop bit (b it length selectable at high level, by uart2cr1), and parity (select parity in uart2cr1; even- or odd-numbered parity by uart2cr1) are added to the transfer data. the transfer da ta formats are shown as follows. figure 13-2 tran sfer data format figure 13-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 13-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 153 TMP86FS49BFG 13.4 transfer rate the baud rate of uart2 is set of uart2cr1. th e example of the baud rate are shown as follows. when tc5 is used as the uart2 transfer rate (when uart2cr1 = ?110?), the transfer clock and transfer rate are determined as follows: transfer clock [hz] = tc5 source clock [hz] / ttreg5 setting value transfer rate [baud] = transfer clock [hz] / 16 13.5 data sampling method the uart2 receiver keeps sampling input using the clock selected by uart2cr1 until a start bit is detected in rxd2 pin input. rt clock starts detecting ?l? level of the rxd2 pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sample d at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to major- ity rule (the data are the same tw ice or more out of three samplings). figure 13-4 data sampling method table 13-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15 01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd2 pin rxd2 pin
page 154 13. asynchronous serial interface (uart2 ) 13.6 stop bit length TMP86FS49BFG 13.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uart2cr1. 13.7 parity set parity / no parity by uart2cr1 and set parity type (odd- or even-numbered) by uart2cr1. 13.8 transmit/receive operation 13.8.1 data transmit operation set uart2cr1 to ?1?. read uart2sr to check uart2sr = ?1?, then write data in td2buf (transmit data buffer). writing data in td2buf zero-clears uart2sr< tbep>, transfers the data to the transmit shift register and the data are sequentiall y output from the txd2 pin. the data output include a one-bit start bit, stop bits whose number is specified in uart2cr1 and a par ity bit if parity addition is specified. select the data transfer baud rate usin g uart2cr1. when data transmit starts, transmit buffer empty flag uart2sr is set to ?1? and an inttxd2 interrupt is generated. while uart2cr1 = ?0? and from when ?1? is wr itten to uart2cr1 to when send data are written to td2buf, the txd2 pin is fixed at high level. when transmitting data, first read uart2sr, then write data in td 2buf. otherwise, uart2sr is not zero-cleared and transmit does not start. 13.8.2 data receive operation set uart2cr1 to ?1?. when data are received vi a the rxd2 pin, the receive data are transferred to rd2buf (receive data buffer). at this time, the data transmitted includes a st art bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rd2buf (receive data buffer). then the receive buffe r full flag uart2sr is set and an intrxd2 interrupt is generated. select the data transfer baud rate using uart2cr1. if an overrun error (o err) occurs when data are received, the da ta are not transferre d to rd2buf (receive data buffer) but discarded; data in the rd2buf are not affected. note:when a receive operation is dis abled by setting uart2cr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 155 TMP86FS49BFG 13.9 status flag 13.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uart2sr is set to ?1?. the uart2sr is cleared to ?0? when the rd2buf is read after reading the uart2sr. figure 13-5 generati on of parity error 13.9.2 framing error when ?0? is sampled as the stop bit in the receive da ta, framing error flag uart2sr is set to ?1?. the uart2sr is cleared to ?0? when th e rd2buf is read after reading the uart2sr. figure 13-6 generati on of framing error 13.9.3 overrun error when all bits in the next data are received while unread data are still in rd2buf, overrun error flag uart2sr is set to ?1?. in this case, the receive data is discarded; data in rd2buf are not affected. the uart2sr is cleared to ?0? when th e rd2buf is read after reading the uart2sr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd2 pin uart2sr intrxd2 interrupt after reading uart2sr then rd2buf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd2 pin uart2sr intrxd2 interrupt after reading uart2sr then rd2buf clears ferr.
page 156 13. asynchronous serial interface (uart2 ) 13.9 status flag TMP86FS49BFG figure 13-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uart2sr is cleared. 13.9.4 receive data buffer full loading the received data in rd2buf sets receive data buffer full flag uart2sr to "1". the uart2sr is cleared to ?0? when the rd2buf is read afte r reading the uart2sr. figure 13-8 generat ion of receive data buffer full note:if the overrun error flag uart2sr is set during the period between reading the uart2sr and read- ing the rd2buf, it cannot be cleared by only reading t he rd2buf. therefore, after reading the rd2buf, read the uart2sr again to check whether or not the overrun error flag which should have been cleared still remains set. 13.9.5 transmit data buffer empty when no data is in the transmit buffer td2buf, that is, when data in td2buf are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag uart2sr is set to ?1?. the uart2sr is cleared to ?0? when the td 2buf is written after reading the uart2sr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd2 pin uart2sr intrxd2 interrupt after reading uart2sr then rd2buf clears oerr. rd2buf uart2sr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd2 pin uart2sr intrxd2 interrupt rd2buf after reading uart2sr then rd2buf clears rbfl.
page 157 TMP86FS49BFG figure 13-9 generation of transmit data buffer empty 13.9.6 transmit end flag when data are transmitted and no data is in td2buf (uart2sr = ?1?), transmit end flag uart2sr is set to ?1?. the uart2sr is cleared to ?0? when the data transmit is started after writing the td2buf. figure 13-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 td2buf txd2 pin uart2sr inttxd2 interrupt after reading uart2sr writing td2buf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd2 pin uart2sr uart2sr inttxd2 interrupt data write for td2buf
page 158 13. asynchronous serial interface (uart2 ) 13.9 status flag TMP86FS49BFG
page 159 TMP86FS49BFG 14. synchronous serial interface (sio1) the serial interfaces connect to an external device via si1, so1, and sck 1 pins. when these pins are used as serial interface, th e output latches for each port should be set to "1". 14.1 configuration figure 14-1 synchronous serial interface (sio) interrupt internal clock input to bus shift register on transmitter shift register on receiver (serial data output) control circuit shift clock internal data bus port (note) (serial data output) port (note) (serial data input) port (note) note: set the register of port correctly for the port assigned as serial interface pins. for details, see the description of the input/output port control register. msb/lsb selection so1 pin si1 pin sio1tdb sio1rdb sck 1 pin intsio1 sio1cr sio1sr
page 160 14. synchronous serial interface (sio1) 14.2 control TMP86FS49BFG 14.2 control the sio is controlled using the serial interface control regi ster (sio1cr). the operating status of the serial inter- face can be inspected by reading the status register (sio1cr). note 1: when sio1cr is set to ?1?, sio1cr, si o1sr register, sio1rdb register and sio1tdb register are initialized. note 2: transfer mode, direction of transfer and serial clock mu st be select during the transfer is stopping (when sio1sr "0"). note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care serial interface control register sio1cr (0020h) 76543210 sios sioinh siom siodir sck (initial value: 0000 0000) sios specify start/stop of transfer 0: stop 1: start r/w sioinh forcibly stops transfer (note 1) 0: ? 1: forcibly stop (automatically cleared to "0" after stopping) siom selects transfer mode 00: transmit mode 01: receive mode 10: transmit/receive mode 11: reserved siodir selects direction of transfer 0: msb (transfer beginning with bit7) 1: lsb (transfer beginning with bit0) sck selects serial clock normal1/2 or idle1/2 modes slow/sleep mode tbtcr = "0" tbtcr = "1" 000 fc/2 12 fs/2 4 fs/2 4 001 fc/2 8 fc/2 8 reserved 010 fc/2 7 fc/2 7 reserved 011 fc/2 6 fc/2 6 reserved 100 fc/2 5 fc/2 5 reserved 101 fc/2 4 fc/2 4 reserved 110 fc/2 3 fc/2 3 reserved 111 external clock (input from sck 1 pin)
page 161 TMP86FS49BFG note 1: the operation error flag (txerr and rxerr) are not autom atically cleared by stopping tr ansfer with sio1cr "0". therefore, set these bits to "0" for clearing these error flag. or set sio1cr to "1". note 2: *: don't care note 1: sio1tdb is write only register. a bit manipulation shoul d not be performed on the transmit buffer register using a read- modify-write instruction. note 2: the sio1tdb should be written after checking sio1sr "1". when sio1sr is "0", the writing data can't be transferred to sio1tdb even if write instruction is executed to sio1tdb note 3: *: don't care serial interface status register sio1sr (0021h) 76543210 siof sef txf rxf txerr rxerr (initial value: 0010 00**) siof serial transfer operation status monitor 0: transfer finished 1: transfer in progress read only sef number of clocks monitor 0: 8 clocks 1: 1 to 7 clocks txf transmit buffer empty flag 0: data exists in transmit buffer 1: no data exists in transmit buffer rxf receive buffer full flag 0: no data exists in receive buffer 1: data exists in receive buffer txerr transfer operation error flag read 0: ? (no error exist) 1: transmit buffer under run occurs in an external clock mode write 0: clear the flag 1: ? (a write of "1" to this bit is ignored) r/w rxerr receive operation error flag read 0: ? (no error exist) 1: receive buffer over run occurs in an external clock mode write 0: clear the flag 1: ? (a write of "1" to this bit is ignored) receive buffer register sio1rdb (0022h) 76543210read only (initial value: 0000 0000) transmit buffer register sio1tdb (0022h) 76543210write only (initial value: **** ****)
page 162 14. synchronous serial interface (sio1) 14.3 function TMP86FS49BFG 14.3 function 14.3.1 serial clock 14.3.1.1 clock source the serial clock can be selected by using sio1cr . when the serial clock is changed, the writing instruction to sio1cr should be executed wh ile the transfer is stopped (when sio1sr ?0?) (1) internal clock setting the sio1cr to other than ?111b? outputs the clock (shown in " table 14-1 serial clock rate (fc = 16 mhz, fs = 32.768khz) ") as serial clock outputs from sck 1 pin. at the before beginning or finishing of a transfer, sck 1 pin is kept in high level. when writing (in the transmit mode) or reading (i n the receive mode) data can not follow the serial clock rate, an automatic-wait function is executed to stop the serial clock au tomatically and hold the next shift operation until reading or writing is completed (shown in " figure 14-2 automatic-wait function (example of transmit mode) "). the maximum time from releasing the automatic-wait function by reading or writing a data is 1 cycle of th e selected serial clock until the serial clock comes out from sck 1 pin. figure 14-2 automatic-wait f unction (example of transmit mode) table 14-1 serial clock rate (fc = 16 mhz, fs = 32.768khz) normal1/2, idle1/2 mode slow1/2, sleep1/2 mode tbtcr = "0" tbtcr = "1" serial clock baud rate sck serial clock baud rate serial clock baud rate 000 fc/2 12 3.906 kbps fs/2 4 2048 bps fs/2 4 2048 bps 001 fc/2 8 62.5 kbps fc/2 8 62.5 kbps reserved ? 010 fc/2 7 125 kbps fc/2 7 125 kbps reserved ? 011 fc/2 6 250 kbps fc/2 6 250 kbps reserved ? 100 fc/2 5 500 kbps fc/2 5 500 kbps reserved ? 101 fc/2 4 1.00 mbps fc/2 4 1.00 mbps reserved ? 110 fc/2 3 2.00 mbps fc/2 3 2.00 mbps reserved ab a0 automatically wait a1 b7 b6 b5 b4 b3 a2 a3 a4 a5 a6 a7 b2 b1 b0 sio1cr so1 pin sio1tdb automatic wait is rel eased by writing sio1tdb sck 1 pin output
page 163 TMP86FS49BFG (2) external clock when an external clock is selected by sett ing sio1cr to ?111b?, the clock via the sck 1 pin from an external source is used as the serial clock. to ensure shift operation, the se rial clock pulse width must be 4/fc or more for both ?h? and ?l? levels. figure 14-3 external clock 14.3.1.2 shift edge the leading edge is used to transmit data, an d the trailing edge is used to receive data. (1) leading edge shift data is shifted on the leading edge of the serial clock (falling edge of the sck 1 pin input/output). (2) trailing edge shift data is shifted on the trailing edge of the serial clock (rising edge of the sck 1 pin input/output). figure 14-4 shift edge t sckl t sckh t sckl, t sckh > 4/fc sck 1 pin 7******* ******** bit7 shift out ***01234 **012345 *0123456 bit5 bit6 bit5 bit6 bit7 67****** 567***** (a) leading edge shift (example of msb transfer) (b) trailing edge shift (example of msb transfer) 01234567 ****0123 *****012 ******01 *******0 ******** bit4 4567**** 34567*** 234567** 1234567* 01234567 bit4 bit3 bit2 bit1 bit0 bit3 bit2 bit1 bit0 sio1cr sck 1 pin shift register so1 pin shift register sck 1 pin si1 pin sio1cr
page 164 14. synchronous serial interface (sio1) 14.3 function TMP86FS49BFG 14.3.2 transfer bit direction transfer data direction can be selected by using sio1 cr. the transfer da ta direction can't be set individually for transm it and receive operations. when the data direction is changed, the writing inst ruction to sio1cr should be executed while the transfer is stopped (when sio1cr= ?0?) figure 14-5 transfer bit dire ction (example of transmit mode) 14.3.2.1 transmit mode (1) msb transmit mode msb transmit mode is selected by setting si o1cr to ?0?, in which case the data is transferred sequentially beginning with the most significant bit (bit7). (2) lsb transmit mode lsb transmit mode is selected by setting sio1cr to ?1?, in which case the data is transferred sequentially beginning with the least significant bit (bit0). 14.3.2.2 receive mode (1) msb receive mode msb receive mode is selected by setting sio1 cr to ?0?, in which case the data is received sequentially beginning with the most significant bit (bit7). (b) lsb transfer a0 a a1 a2 (a) msb transfer a3 a4 a5 a6 a7 shift out a7 a a6 a5 a4 a3 a2 a1 a0 shift out siocr sck 1 pin sio1tdb so1 pin sio1cr sck 1 pin sio1tdb so1 pin
page 165 TMP86FS49BFG (2) lsb receive mode lsb receive mode is selected by setting sio1 cr to ?1?, in which case the data is received sequentially beginning with the least significant bit (bit0). 14.3.2.3 transmit/receive mode (1) msb transmit/receive mode msb transmit/receive m ode are selected by setting sio1cr to ?0? in which case the data is transferred sequentially be ginning with the most significant bit (bit7) and the data is received sequentially beginning with the most significant (bit7). (2) lsb transmit/receive mode lsb transmit/receive mode are se lected by setting sio1 cr to ?1?, in which case the data is transferred sequentially be ginning with the least significant bit (bit0) and the data is received sequentially beginning with the least significant (bit0). 14.3.3 transfer modes transmit, receive and transmit/receive mode are selected by using sio1cr. 14.3.3.1 transmit mode transmit mode is selected by writing ?00b? to sio1cr. (1) starting the transmit operation transmit mode is selected by se tting ?00b? to sio1cr. seri al clock is selected by using sio1cr. transfer di rection is selected by using sio1cr. when a transmit data is written to the transm it buffer register (sio1tdb), sio1sr is cleared to ?0?. after sio1cr is set to ?1?, sio1sr is set synchronously to ?1? the falling edge of sck 1 pin. the data is transferred sequentially starting from so1 pin with the directio n of the bit specified by sio1cr, synchronizing with the sck 1 pin's falling edge. sio1sr is kept in high level, between the first clock falling edge of sck 1 pin and eighth clock falling edge. sio1sr is set to ?1? at the rising edge of pin after the data written to the sio1tdb is transferred to shift register, then the intsio1 interrupt request is generated, synchronizing with the next falling edge on sck 1 pin. note 1: in internal clock operation, when sio1cr is set to "1", transfer mode does not start with- out writing a transmit data to the transmit buffer register (sio1tdb). note 2: in internal clock operation, when the sio1cr is set to "1", sio1tdb is transferred to shift register after maximum 1-cycl e of serial clock frequency, then a serial clock is output from sck 1 pin. note 3: in external clock operation, when the falling edge is input from sck 1 pin after sio1cr is set to "1", sio1tdb is transferred to shift register immediately.
page 166 14. synchronous serial interface (sio1) 14.3 function TMP86FS49BFG (2) during the transmit operation when data is written to sio1tdb, sio1sr is cleared to ?0?. in internal clock operation, in case a next transmit data is not written to sio1tdb, the serial clock stops to ?h? level by an automatic-wait function when all of the bit set in the sio1tdb has been transmitted. automatic-wait function is released by writing a transmit data to sio1tdb. then, trans- mit operation is restarted after maximum 1-cycle of serial clock. when the next data is written to the sio1tdb before termination of previous 8-bit data with sio1sr ?1?, the next data is continuously transferred after transmission of previous data. in external clock operation, afte r sio1sr is set to ?1?, the transmit data must be written to sio1tdb before the shift operation of the next data begins. if the transmit data is not written to sio1tdb, transmit error occurs immediately after shift opera- tion is started. then, intsio1 interrupt request is generated after sio1sr is set to ?1?. (3) stopping the transmit operation there are two ways for st opping transmits operation. ? the way of clearing sio1cr. when sio1cr is cleared to ?0?, transmit operat ion is stopped after all transfer of the data is finished. when transmit operation is finished, sio1sr is cleared to ?0? and so1 pin is kept in high level. in external clock operation, sio1cr must be cleared to ?0? before sio1sr is set to ?1? by beginning next transfer. ? the way of setting sio1cr. transmit operation is stopped immediately afte r sio1cr is set to ?1?. in this case, sio1cr, sio1sr register, sio1rd b register and sio1tdb register are ini- tialized. figure 14-6 example of inte rnal clock and msb transmit mode a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 c7 a7 b0 c6 c5 c4 c3 c2 c1 c0 a b c automatic wait start shift operation start shift operation start shift operation writing transmit data b writing transmit data a writing transmit data c clearing sios sio1cr sio1sr

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